On a novel method of impact by a front-end-coated bullet to evaluate the interface adhesion between film and substrate

A preliminary experiment was carried out to validate the feasibility of the method of impact by a front-end-coated bullet to evaluate the interface adhesion between film and substrate. The theoretical description of the initiation, propagation and evolution of the stress pulse during impact was generalized and formulized. The effects of the crucial parameters on the interface stress were further investigated with FEM. The results found the promising prospect of the application of such a method and provided useful guidance for experimental design.

A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF-DC Rectifier

This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mu m 2P4M CMOS technology. The whole chip occupies a die area of 490 x 780 mu m(2) and consumes only 2.1 mu W in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a - 14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.

A wide-band front-end for terrestrial and cable receptions

In this paper, a wide-band low noise amplifier, two mixers and a VCO with its buffers implemented in 50GHz 0.35 mu m SiGe BiCMOS technology for dual-conversion digital TV tuner front-end is presented. The LNA and up-converting mixer utilizes current injection technology to achieve high linearity. Without using inductors, the LNA achieves 0.1-1GHz wide bandwidth and 18.8-dB gain with less than 1.4-dB gain variation. The noise figure of the LNA is less than 5dB and its 1dB compression point is -2 dBm. The IIP3 of two mixers is 25-dBm. The measurement results show that the VCO has -127.27-dBc/Hz phase noise at 1-MHz offset and a linear gain of 32.4-MHz/V between 990-MHz and 1.14-GHz. The whole chip consume 253mW power with 5-V supply.

A CMOS front-end circuit for SONET OC-96 receiver

An optical receiver front-end for SONET OC-96 receivers was analyzed and designed in 0.18 mu m CMOS process. It consists of a transimpedance amplifier (TIA) and a limiting amplifier (LA). The TIA takes a fully differential configuration, and regulated cascode (RGC) input stage is implemented. The LA was realized by five cascaded identical gain stages with active inductor load. The TIA achieved 4.2GHz bandwidth for 0.5pF photodiode (PD) capacitance and 1.2k 0 transimpedance gain. The LA achieved 5.4GHz bandwidth and 29dB voltage gain. The optical sensitivity is -19dBm at 5-Gb/s for a bit-error rate of 10(-12), and it dissipates 45.5mW for I.8V supply.

5.2 GHz variable-gain amplifier and power amplifier driver for WLAN IEEE 802.11a transmitter front-end

A 5.2 GHz variable-gain amplifier (VGA) and a power amplifier (PA) driver are designed for WLAN IEEE 802.11a monolithic RFIC. The VGA and the PA driver are implemented in a 50 GHz 0.35 μm SiGe BiCMOS technology and occupy 1.12×1.25 mm~2 die area. The VGA with effective temperature compensation is controlled by 5 bits and has a gain range of 34 dB. The PA driver with tuned loads utilizes a differential input, single-ended output topology, and the tuned loads resonate at 5.2 GHz. The maximum overall gain of the VGA and the PA driver is 29 dB with the output third-order intercept point (OIP3) of 11 dBm. The gain drift over the temperature varying from -30 to 85℃ converges within±3 dB. The total current consumption is 45 mA under a 2.85 V power supply.

同步加速器高频系统前端控制器改进设计；Improvement Design of RF Front-end Controller for Synchrotron RF System

介绍了在CSR同步加速器高频控制系统改进项目中,高频前端控制器的改进设计。根据系统改进的具体要求,采用DSP+FPGA双电路板的体系结构,对高频前端控制器各个部分做了详细的设计,并给出了具体的资源消耗结果和设计图。

EVALUATION OF FILM-SUBSTRATE ADHESION VIA IMPACT USING COATED BULLETS

A method was devised to evaluate the adhesion between a film and a substrate. A front-end coated bullet is accelerated by a gas gun and hits the substrate of the specimen under test. The impact generates a compressive stress pulse that propagates toward the film. After transmission through the interface, part of the pulse is reflected on the free surface of the film, and tensile stress arises at the film-substrate interface, possibly inducing debonding of the film. This dynamic process was demonstrated analytically and simulated numerically by the finite element method. The results validate the initial concept and lay the foundation for further optimization of this method.

高功率激光装置前端系统激光脉冲的时间整形及修正技术

针对激光惯性约束聚变实验研究对高功率激光驱动器前端系统复杂时间形状种子激光脉冲的需求, 应用孔径耦合带状线集成波导整形系统设计了满足需要的前端整形激光脉冲。用一种新方法精确计算了孔径耦合带状线电脉冲整形器的耦合系数和孔径宽度的数值关系, 并针对高衬比度整形激光脉冲的需求, 提出了高衬比度双极型集成波导整形系统方案。由该系统可以得到100 ps脉冲前沿、1～3 ns脉冲宽度可调、高衬比度(大于100∶1)、光滑无纹波调制、可精确满足神光II八路及第九路装置需求的前端整形激光脉冲。

支持JSR286规范的Portlet协作框架的设计与实现

Portlet是具有用户界面的可与用户多次交互的Web组件。随着Portal和Portlet在企业中的广泛应用，仅仅将各种应用和数据通过Portlet集成到Portal中已经不能满足用户的需求。用户希望这些应用之间能够相互协作，以利用现有应用组建新的业务流程。Portlet协作是指两个或多个Portlet进行信息交换并使用这些信息的能力。目前协作功能的实现方式可以分为两种：基于后端(back-end)的实现方式与基于前端(front-end)的实现方式。在这两种协作实现方式的基础上，本文提出了两种Portlet协作框架。 本文提出一种基于事件的Portlet前端协作模型，通过引入此模型，解决了Portlet前端协作中客户端与服务器端无法交互的困难，使协作动作由客户端和服务器端共同完成。基于此模型提供给开发者一种可扩展的协作框架，利用JavaScript技术使得协作的Portlet在客户端“相知”，协作的行为在客户端触发，Portlet获得协作数据后使用Ajax技术请求服务器端的资源，服务器端使用JSR286规范定义的资源服务接口响应用户的请求，进而动态更新界面。 当前的Portlet后端协作方式依赖于特定的Portal产品，针对这点不足，本文在JSR286规范定义的事件及共享渲染参数协作机制基础上，实现了一个Portlet后端协作框架。在该框架中协作服务使用消息队列保存待处理的消息，Portlet 容器作为中介实现发布事件的Portlet和订阅事件的Portlet之间松散耦合。Portlet监听协作事件，事件触发后调用事件协作服务发布事件，为了提高协作的并发性，事件协作服务使用多线程处理协作事件。该协作框架与JSR286规范兼容，具有良好的可移植性。 本文对这两种Portlet协作框架进行了实现，并将其应用于中科院软件所自主开发的门户产品OncePortal中。本文重构了OncePortal系统，给出了框架的体系结构与系统接口，描述了框架的各功能模块，并详细讨论了Portlet协作框架中的关键技术，包括事件协作流程的描述、事件处理过程、多级事件流等。

Multi-strip MRPCs for FOPI

During the last years FOPI has developed a new ToF system as an upgrade of the existing detector based on Multi-strip Multi-gap Resistive Plate Chambers (MMRPCs). The intention is to increase the charged Kaon identification up to a laboratory momentum of 1 GeV/c and to enhance the azimuthal detector granularity. The new ToF barrel has an active area of 5 m(2) with 2400 individual strips (900 x 1.6 mm(2)) [A. Schuttauf, et al., Nucl. Phys. B 158 (2006) 52] which are read out on both sides by a custom designed electronics [M. Ciobanu, et al., IEEE Trans. Nucl. Sci. NS-54 (4) (2007) 1201; K. Koch, et al., IEEE Trans. Nucl. Sci. NS-52(3) (2005) 745]. To reach the envisaged goal a time resolution of 100 ps is needed, at a flight path of 1-1.3 m. Due to the rare production of the K- at SIS energies the efficiency of the MMRPCs has to be above 95%. We report on measurements with the detectors and electronics from the mass production line. For this purpose we used a proton beam at 2.0 and 1.25 GeV, at rates between 0.1 and 5 kHz/cm(2) to determine the timing, efficiency and rate capability of the MMRPCs

A low noise charge sensitive preamplifier with switch control feedback resistance

In this paper, the design and analysis of a new low noise charge sensitive preamplifier for silicon strip, Si(Li), CdZnTe and CsI detectors etc. with switch control feedback resistance were described, the entire system to be built using the CMOS transistors. The circuit configuration of the CSP proposed in this paper can be adopted to develop CMOS-based Application Specific Integrated Circuit further for Front End Electronics of read-out system of nuclear physics, particle physics and astrophysics research, etc. This work is an implemented design that we succeed after a simulation to obtain a rise time less than 3ns, the output resistance less than 94 Omega and the linearity almost good.

The Compact Pulsed Hadron Source: A Design Perspective

During the past. decades, large-scale national neutron sources have been developed in Asia, Europe, and North America. Complementing such efforts, compact hadron beam complexes and neutron sources intended to serve primarily universities and industrial institutes have been proposed, and some have recently been established. Responding to the demand in China for pulsed neutron/proton-beam platforms that are dedicated to fundamental and applied research for users in multiple disciplines from materials characterization to hadron therapy and radiography to accelerator-driven sub-critical reactor systems (ADS) for nuclear waste transmutation, we have initiated the construction of a compact, yet expandable, accelerator complex-the Compact Pulsed Hadron Source (CPHS). It consists of an accelerator front-end (a high-intensity ion source, a 3-MeV radio-frequency quadrupole linac (RFQ), and a 13-MeV drift-tube linac (DTL)), a neutron target station (a beryllium target with solid methane and room-temperature water moderators/reflector), and experimental stations for neutron imaging/radiography, small-angle scattering, and proton irradiation. In the future, the CPHS may also serve as an injector to a ring for proton therapy and radiography or as the front end to an ADS test facility. In this paper, we describe the design of the CPHS technical systems and its intended operation.

中子墙探测器前端电子学研究

随着国家大科学工程兰州重离子加速器冷却储存环(HIRFL-CSR)建成，CSRm实验探测系统也正在建设当中。CSRm实验探测系统由外靶系统和内靶系统构成。外靶系统主要有γ探测器、多丝漂移室（MWDC）、ToF墙(ToF Wall)、中子墙（Neutron Wall）等探测器组成，主要用于核物理研究。其中，用于探测中子的中子墙探测器是外靶系统中的一个重要组成部分，它有252个探测单元，每一个探测器单元都要求既有很好的能量分辨，也要有很好的时间分辨，同时还要求数据获取率达到每秒几千个事件。对于这样先进的探测器和大型实验探测系统采用传统的电子学仪器和方法已经无法构成读出电子学系统，建造与之相配的读出电子学系统是极为重要的和亟待解决的工作。为此，我们设计研发适合于中子墙探测器这样的大型闪烁体探测器的前端电子学读出系统。包括三大部分：16道电荷幅度转换电路（QAC），16道时间幅度转换电路（TAC）和有效信号判断电路。本论文的主要内容如下：在第一章绪论中，介绍了论文课题的出发点以及课题的意义，并对课题的背景进行了介绍。第二章介绍我们所自行设计的中子墙探测器的特点、结构。分析了中子墙探测器的输出信号的特点以及对后续前端电子学读出系统的要求。第三章是本论文两大核心部分之一，是本论文的创新点所在。主要介绍了我们电荷幅度转换的新方法，结合通常的QAC电路方法和具体的实际情况，我们自行提出了一种新的QAC电路，包括以下几个部分：差分输入电路、电流分割、上下恒流源、门控电流积分器。我们的创新点在于，我们用上下恒流源分别代替了通常QAC中作为电流分配的电流镜像和作为电流基准的电阻，这样一来更容易得到比较稳定的偏置电流，从而能够得到更高的转换精度。第四章是本论文的另外一个核心部分，首先我们论述了核电子学时间测量的几种方法，在对它们进行对比后，结合中子墙的实际特点，我们确定了采用起停型的TAC方法。然后介绍了TAC的原理，以及具体的电路结构。第五章主要的内容是对我们整个电路的逻辑电路进行了详细的介绍，它包括16道QAC和16道TAC的积分控制信号和泄放控制信号的产生电路以及有效信号判断电路。详细论述了这些逻辑关系以及如何在CPLD实现，并且给出了仿真结果。第六章详细讨论了我们在设计PCB板时遇到的问题及其解决方法。第七章介绍了多路QAC和多路TAC主要指标及其测试方法、步骤、结果并给出了误差分析。在总结部分我们回顾了我们整个工作的过程，介绍了论文的主要成果和创新点以及对于整个CSR工程的意义。本论文的创新点： 1、提出了一种新型的QAC电路。 2、将16道QAC和16道TAC以及有效信号判断电路集成在一个插件中提高了电路的集成度，并为最终集成在一片ASIC芯片中打下坚实的基础。 3、用可编程逻辑器件代替ECL器件来构建逻辑电路，降低了功耗和成本并提高了系统的可靠性

HIRFL-CSR束流位置监测系统的前端电子学研究

国家大科学工程兰州重离子加速器冷却储存环(HIRFL-CSR)已经建成，在CSR调试过程中各系统均要保证加速器稳定运行，而束流诊断系统的稳定可靠运行对顺利完成调试任务具有重要意义。系统可测得束流的能量、强度、位置、相位、剖面和发射度等参数。对这些参数的准确测量是实现CSR稳定运行和各部分之间匹配的必要手段。而束流参数一般都是通过采集可由计算机处理的电信号，并经过合理的分析得到的。因此对前端电子学系统的研究必不可少。本论文将围绕HIRFL-CSR束流诊断系统的子系统——束流位置监测系统的前端电子学设计来展开。由于我所冷却储存环的束流强度弱（最低100nA），现场的噪声和干扰较大，束流监测系统探测单元的输出信号很容易被噪声淹没，所以设计一个合适的前端电子学电路十分必要，而且需要采用一些特殊的微弱信号检测方法。通过对微弱信号检测方法的研究和学习，我们先后采用了两种处理方法，对淹没于噪声中的微弱信号幅值进行检测。第一种方法是基于宽带放大和峰值保持电路来完成对信号峰值的检测；第二种方法是基于外差式技术与锁定放大方法来实现信号峰值的检测。本论文对这两种处理方法和所涉及到的电子学电路原理进行了详细的阐述。论文的主要内容如下：第一章主要针对课题的研究背景来展开。简单介绍了HIRFL-CSR工程，及其束流诊断系统，最后结合束流诊断系统的子系统—束流位置检测系统的前端电子学电路，提出了微弱信号检测方法。第二章介绍了微弱信号检测技术，重点分析了噪声的种类和抑制噪声的处理方法。第三章对我们在束流位置检测系统的前端电子学电路中，采用的第一种处理方法—基于宽带方式的处理方法，作了详细的介绍。主要包括下面几个单元电路： 高阻输入形式和低阻输入形式的低噪声宽带放大器、高速窄脉冲信号峰值保持电路，慢前沿信号峰值保持电路。第四章对我们在束流位置检测系统的前端电子学电路中，采用的第二种处理方法—基于窄带方式的处理方法，作了详细的介绍。重点分析了外差式锁定放大电路中的频率合成器、频谱搬移电路和低通滤波电路。第五章围绕巴特沃思型滤波器的设计展开。主要介绍了低通、高通和带通三种滤波器的理论计算，并作了相应的功能仿真。第六章针对我们涉及到的所有电路的PCB设计，作了相关的分析和总结。第七章对外差式锁定放大电路的实验室参数测试方法、步骤和偏差分析作了详细的介绍。第八章对总结回顾了几年来科研学习所取得的阶段性成果，并对今后的工作方向做了一个简单的计划