The design and verification of FPGA CAD toolset

This paper introduces a complete CAD toolset for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform. Compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. The FPGA CAD tool verification flow using Formality is presented in detail. Using plug-in technology, we have developed an integrated FPGA design kit to incorporate all tools together.

Real-time data processing of interferential imaging spectrometer based on FPGA

Based on the data processing technologies of interferential spectrometer, a sort of real-time data processing system on chip of interferential imaging spectrometer was studied based on large capacitance and high speed field programmable gate array( FPGA) device. The system integrates both interferograrn sampling and spectrum rebuilding on a single chip of FPGA and makes them being accomplished in real-time with advantages such as small cubage, fast speed and high reliability. It establishes a good technical foundation in the applications of imaging spectrometer on target detection and recognition in real-time.

星载激光测距仪的高精度时间间隔测量单元

高精度时间间隔测量单元(TIU)是星载激光测距仪的关键部件。基于现场可编程门阵列(FPGA)研制出了满足星载要求的高精度、高集成度时间间隔测量单元。该单元采用数字计数法结合数字延迟线插入法的技术,在0.5～10 km的测量距离范围内,时间分辨率为500 ps。通过地面检测,在全程范围内保持了良好的线性度,标准偏差小于270 ps。该单元同时具备测量脉冲回波宽度的能力,可以获取目标的脉冲展宽信息。由于单元选用的元器件都具有航天产品性能,因此其设计和技术指标可满足星载激光测距仪的应用。

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

40Gb/s甚短距离并行光传输信号格式转换模块实现

根据OIF-VSR5-01.0的CWDM协议,对40 Gb/s甚短距离(VSR)并行光传输电信号转换实现原理和方法进行了研究,在高速的可编程逻辑器件FPGA(field programmable gate array)上,使用硬件描述语言,完成了对时钟数据恢复、信道去斜移、64 b/66 b转换、帧对准和扰码与解扰等功能模块的设计,实现了SFI-5接口与OIF-VSR5-01.0接口电信号格式的相互转换,建立了符合4信道CWDM协议的IP核.

FPGA在偏振耦合测试仪中的应用

在偏振耦合测试仪的PCI接口数据采集系统中,现场可编程门阵列(FieldProgramableGateArray)实现了对模/数器件的控制功能,同时完成了与PCI总线控制器间的数据接口功能。应用自顶向下的设计思想,完成了FPGA内部的逻辑设计,并对其逻辑功能进行了仿真验证,给出了FPGA数据采集时的测试时序图。应用FPGA实现的数据采集系统可以检测出偏振耦合检测仪中的微弱干涉光信号。

Mode theory and analysis of planar array waveguides

Bloch modes can be excited in planar array due to its periodic lateral refractive index. The power coupled into each eigenmode of the array waveguides is calculated through the overlap integrals of the input field with the eigenmode fields of the coupled infinite array waveguides projected onto the x-axis. Low losses can be obtained if the transition from the array to the free propagation region is adiabatic. Due to the finite resolution of lithographic process the gap between the waveguides will stop abruptly, however, when the waveguides come into too close together. Calculation results show that losses will occur at this discontinuity, which are dependent on the ratio of the gap between the waveguides and grating pitch and on the confinement of field in the array waveguides. Tapered waveguides and low index contrast between the core and cladding layers can lower the transmitted losses.

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

Generation of near-field hexagonal array illumination with a phase grating

A hexagonal array not only is a nature-preferred pattern but also is widely used in optoelectronical materials and devices. We report a simple method of hexagonal array illumination based on the Talbot effect that has a theoretical efficiency of 100%. An experimental efficiency of 90.6% with a binary phase (0, pi) hexagonal grating is given. This method should be highly interesting for applications of hexagonal array illumination in optical devices as well as in other hexagonal cells. (C) 2002 Optical Society of America.

Near-field hexagonal array illumination based on fractional Talbot effect

Hexagonal array is a basic structure widely exists in nature and adopted by optoclectronic device. A phase plate based on the fractional Talbot effect that converts a single expanded laser beam into a regular hexagonal array of uniformly illuminated apertures with virtually 100% efficiency is presented. The uniform hexagonal array illumination with a fill factor of 1/12 is demonstrated by the computer simulation. (C) 2006 Elsevier GmbH. All rights reserved.

Single-electron multiple-valued memory using ultra-small floating gate metal-oxide-semiconductor field effect transistor

This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

In-plane stray field induced spin-filtering in a two-dimensional electron gas under the modulation of surface ferromagnetic dual-gate

Based upon a hybrid ferromagnet/semiconductor structure consisting of two-dimensional electron gas and a pair of surface ferromagnetic stripes on top, we have theoretically investigated the effect of in-plane stray field omitted frequently in previous studies on the spin-dependent ballistic transport properties in hybrid structure. It is demonstrated here that, in combination with an external-controllable electrostatic modulation, the concerned structure shows a similar function as a lateral spin-polarized resonant tunneling device, where the strong spin-filtering effect occurs and nearly single-mode polarization is anticipated for the proper modulation. More importantly, the spin polarity of transmission electron can be easily transferred from one extreme to the other by switching the magnetization of stripes, showing the promising application as an efficient spin aligner in the developing semiconductor spintronics.

Quasi-Dammann Grating With Proportional Intensity Array Spots

A quasi-Dammann grating is proposed to generate array spots with proportional-intensity orders in the far field. To describe the performance of the grating, the uniformities of the array spots are redefined. A two-dimensional even-sampling encode scheme is adopted to design the quasi-Dammann grating. Numerical solutions of the binary-phase quasi-Dammann grating with proportional-intensity orders are given. The experimental results with a third-order quasi-Dammann grating, which has an intensity proportion of 3:2:1 from zero order to second order, are presented. (C) 2008 Optical Society of America

Temporal confinement and enhancement of high-order harmonic emission with a synthesized laser field

We demonstrated that a synthesized laser field consisting of an intense long (45 fs, multi-optical-cycle) laser pulse and a weak short (7 fs, few-optical-cycle) laser pulse can control the electron dynamics and high-order harmonic generation in argon, and generate extreme ultraviolet supercontinuum towards the production of a single strong attosecond pulse. The long pulse offers a large amplitude field, and the short pulse creates a temporally narrow enhancement of the laser field and a gate for the highest energy harmonic emission. This scheme paves the way to generate intense isolated attosecond pulses with strong multi-optical-cycle laser pulses.