数字制造环境下的加工过程仿真验证技术研究

生产线数字制造环境是数字化工厂的核心 ,而加工过程的仿真与验证技术构成生产线数字系统的底层结构与制造过程数字化分析的主要内容。分析了目前加工过程在几何仿真与物理仿真方面的研究情况、研究方法与存在问题 ,就该项技术向生产线数字制造环境融合的关键技术 ,即综合设备数字样机的完整数字加工环境的建立及加工过程仿真与上层制造环境的信息集成等进行分析与研究

Digital simulation in a thin layer spectroelectrochemical cell with minigrid platinum electrode by microregion approximation explicit finite difference method

The microregion approximation explicit finite difference method is used to simulate cyclic voltammetry of an electrochemical reversible system in a three-dimensional thin layer cell with minigrid platinum electrode. The simulated CV curve and potential scan-absorbance curve were in very good accordance with the experimental results, which differed from those at a plate electrode. The influences of sweep rate, thickness of the thin layer, and mesh size on the peak current and peak separation were also studied by numerical analysis, which give some instruction for choosing experimental conditions or designing a thin layer cell. The critical ratio (1.33) of the diffusion path inside the mesh hole and across the thin layer was also obtained. If the ratio is greater than 1.33 by means of reducing the thickness of a thin layer, the electrochemical property will be far away from the thin layer property.

Cascaded Fresnel digital hologram and its application to watermarking

A cascaded Fresnel digital hologram (CFDH) is proposed, together with its mathematical derivation. Its application to watermarking has been demonstrated by a simulation procedure, in which the watermark image to be hidden is encoded into the phase of the host image. The watermark image can be deciphered by the CFDH setup, the reconstructed image shows good quality and the error is almost close to zero. Compared with previous technique, this is a lensless architecture which minimizes the hardware requirement, and it is used for the encryption of digital image.

Watermarks encrypted in the cascaded Fresnel digital hologram

A cascaded Fresnel digital hologram (CFDH) is proposed, together with its mathematical derivation. Its application to watermarking has been demonstrated by a simulation procedure, in which the watermark image to be hidden is encoded into the phase of the host image. The watermark image can be deciphered by the CFDH setup, the reconstructed image shows good quality and the error is almost closed to zeros. Compared with previous technique, this is a lensless architecture, which minimizes the hardware requirement. (c) 2006 Elsevier GmbH. All rights reserved.

Phase-shifting apodizer for next-generation digital versatile disk

The next generation digital versatile disk (DVD) using blue lasers will have a capacity of 13 to 15 Gbytes. Compared with current DVD, the wavelength will be shorter and the numerical aperture (NA) will be higher. But with the increase of NA and decrease of wave length, the depth of focus (DOF) decrease rapidly, which makes it hard for the servo-system to track. We propose an optimized three-portion phase-shifting apodizer to increase the depth of focus and at the same time minimize the spot size, which makes the DOF of next generation DVD comparable to current DVD. The simulation result shows that an optical system with this apodizer also has a good defocus characteristic. (C) 2001 Society of Photo-Optical Instrumentation Engineers.

Crosstalk analysis of a fiber laser sensor array system based on digital phase-generated carrier scheme

A detailed study on analyzing the crosstalk in a wavelength division multiplexed fiber laser sensor array system based on a digital phase generated carrier interferometric interrogation scheme is reported. The crosstalk effects induced by the limited optical channel isolation of a dense wavelength division demultiplexer (DWDM) are presented, and the necessary channel isolation to keep the crosstalk negligible to the output signal was calculated via Bessel function expansion and demonstrated by a two serial fiber laser sensors system. Finally, a three-element fiber laser sensor array system with a 50-dB channel-isolation DWDM was built up. Experimental results demonstrated that there was no measurable crosstalk between the output channels.

Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as-follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than uW; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

Improved digital processing method used for image motion measurement based on hybrid opto-digital joint transform correlator

Hybrid opto-digital joint transform correlator (HODJTC) is effective for image motion measurement, but it is different from the traditional joint transform correlator because it only has one optical transform and the joint power spectrum is directly input into a digital processing unit to compute the image shift. The local cross-correlation image can be directly obtained by adopting a local Fourier transform operator. After the pixel-level location of cross-correlation peak is initially obtained, the up-sampling technique is introduced to relocate the peak in even higher accuracy. With signal-to-noise ratio >= 20 dB, up-sampling factor k >= 10 and the maximum image shift <= 60 pixels, the root-mean-square error of motion measurement accuracy can be controlled below 0.05 pixels.