High-Strength Composite Fibers: Realizing True Potential of Carbon Nanotubes in Polymer Matrix through Continuous Reticulate Architecture and Molecular Level Couplings

Carbon nanotubes have unprecedented mechanical properties as defect-free nanoscale building blocks, but their potential has not been fully realized in composite materials due to weakness at the interfaces. Here we demonstrate that through load-transfer-favored three-dimensional architecture and molecular level couplings with polymer chains, true potential of CNTs can be realized in composites as Initially envisioned. Composite fibers with reticulate nanotube architectures show order of magnitude improvement in strength compared to randomly dispersed short CNT reinforced composites reported before. The molecular level couplings between nanotubes and polymer chains results in drastic differences in the properties of thermoset and thermoplastic composite fibers, which indicate that conventional macroscopic composite theory falls to explain the overall hybrid behavior at nanoscale.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Guest inducing p-sulfonatocalix[4] arene into three-dimensional capsule architecture and a mixed A-B double layer framework

The reactions of sodium p-sulfonatocalix[4]arene (Na5L) and terbium/europium(III) chloride in the presence of pyrazine-N,N'-dioxide (PNNO) in aqueous solutions gave the crystalline complexes 1 and 2. Both structures contain molecular capsules of p-sulfonatocalix[4] arene with PNNO as guest molecules in the cavity of the calix[4]arenes. The molecular capsules are connected through sodium and terbium (or europium) centers forming a three-dimensional framework.

Self-assembled 3D microflowery In(OH)(3) architecture and its conversion to In2O3

Using sodium dodecyl sulfate (SDS), a 3D microflowery indium hydroxide [In(OH)(3)] structure assembled from 2D nanoflakes was fabricated in a large quantity via a hydrothermal approach at relative low temperature. The obtained In(OH)(3) flowers exhibited a narrow size range between 4 and 6 mu m. The properties of these composites were characterized by XRD, EDX, FE-SEM, TEM, SAED, and TGA. In this work, both the use of urea and SDS and the amounts of these components played important roles in the formation of In(OH)3 with different nanostructures.

Self-assembly of lambda-DNA networks/Ag nanoparticles: Hybrid architecture and active-SERS substrate

In this article, highly rough and stable surface enhanced Raman scattering (SERS)-active substrates had been fabricated by a facile layer by-layer technique. Unique lambda-DNA networks and CTAB capped silver nanoparticles (AgNP) were alternatively self-assembled on the charged mica surface until a desirable number of bilayers were reached. The as-prepared hybrid architectures were characterized by UV-vis spectroscopy, tapping mode atomic force microscopy (AFM) and confocal Raman microscopy, respectively.

Stress-facilitated LTD induces output plasticity through a synchronized-spikes and spontaneous unitary discharges the CA1 region of the hippocampus

Long-term potentiation (LTP) and long-term depression (LTD) of the excitatory synaptic inputs plasticity in the hippocampus is believed to underlie certain types of learning and memory. Especially, stressful experiences, well known to produce long-lasting strong memories of the event themselves, enable LTD by low frequency stimulation (LFS, 3 Hz) but block LTP induction by high frequency stimulation (HFS, 200 Hz). However, it is unknown whether stress-affected synaptic plasticity has an impact on the output plasticity. Thus, we have simultaneously studied the effects of stress on synaptic plasticity and neuronal output in the hippocampal CA1 region of anesthetized Wistar rats. Our results revealed that stress increased basal power spectrum of the evoked synchronized-spikes and enabled LTD induction by LFS. The induction of stress-facilitated LTD but not LFS induced persistent decreases of the power spectrum of the synchronized-spikes and the frequency of the spontaneous unitary discharges; However, HFS induced UP in non-stressed animals and increased the power spectrum of the synchronized-spikes, without affecting the frequency of the spontaneous unitary discharges, but HFS failed to induce UP in stressed animals without affecting the power spectrum of the synchronized-spikes and the frequency of the spontaneous unitary discharges. These observations that stress-facilitated LTD induces the output plasticity through the synchronized-spikes and spontaneous unitary discharges suggest that these types of stress-related plasticity may play significant roles in distribution, amplification and integration of encoded information to other brain structures under stressful conditions. (C) 2004 Elsevier Ireland Ltd and The Japan Neuroscience Society. All rights reserved.

Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon's expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated.

Architecture research and hardware implementation on simplified neural computing system for face identification

This paper describes a special-purpose neural computing system for face identification. The system architecture and hardware implementation are introduced in detail. An algorithm based on biomimetic pattern recognition has been embedded. For the total 1200 tests for face identification, the false rejection rate is 3.7% and the false acceptance rate is 0.7%.

The design of cascaded resistors in a new analog switch two-step ADC architecture

In this paper we introduce a new Half-flash analog switch ADC architecture. And we discuss two methods to design the values of the cascaded resistors which generate the reference voltages. Derailed analysis about the effect of analog switches and comparators on reference voltages, and the methods to set the resistor values and correspond;ng voltage errors are given.