中间件中读写器适配器设计

本文在介绍了RFID中间件技术研究现状与RFID中间件体系结构的基础上,针对企业应用环境中多标准、多协议谈写器并存的复杂现状,重点介绍了一种能够控制多种RFID硬件读写器的适配器原型。在本文的最后,简要的介绍了利用拓展后的适配器原型控制两种RFID读写器读取RFID标签的实验情况,验证了该适配器原型的有效性、可重用性与可拓展性。

被动反射式900MHz RFID 电路系统研究

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

Lifetime distribution of spontaneous emission from line antennas in two-dimensional quasi-periodic photonic crystals

We investigate the lifetime distribution functions of spontaneous emission from line antennas embedded in finite-size two-dimensional 12-fold quasi-periodic photonic crystals. Our calculations indicate that two-dimensional quasi-periodic crystals lead to the coexistence of both accelerated and inhibited decay processes. The decay behaviors of line antennas are drastically changed as the locations of the antennas are varied from the center to the edge in quasi-periodic photonic crystals and the location of transition frequency is varied.

A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF-DC Rectifier

This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mu m 2P4M CMOS technology. The whole chip occupies a die area of 490 x 780 mu m(2) and consumes only 2.1 mu W in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a - 14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.

Spontaneous emission lifetime distribution of infinite line antennas in two-dimensional photonic crystals with finite size

The authors calculate the lifetime distribution functions of spontaneous emission from infinite line antennas embedded in two-dimensional disordered photonic crystals with finite size. The calculations indicate the coexistence of both accelerated and inhibited decay processes in disordered photonic crystals with finite size. The decay behavior of the spontaneous emission from infinite line antennas changes significantly by varying factors such as the line antennas' positions in the disordered photonic crystal, the shape of the crystal, the filling fraction, and the dielectric constant. Moreover, the authors analyze the effect of the degree of disorder on spontaneous emission. (c) 2007 American Institute of Physics.

A novel ultra low power temperature sensor for UHF RFID tag chip

A novel ultra low power temperature sensor for UHF RFID tag chip is presented. The sensor consists of a constant pulse generator, a temperature related oscillator, a counter and a bias. Conversion of temperature to digital output is fulfilled by counting the number of the clocks of the temperature related oscillator in a constant pulse period. The sensor uses time domain comparing, where high power consumption bandgap voltage references and traditional ADCs are not needed. The sensor is realized in a standard 0.18 mu m CMOS process, and the area is only 0.2mm(2). The accuracy of the temperature sensor is +/- 1 degrees C after calibration. The power consumption of the sensor is only 0.9 mu W.

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

High efficiency RFID UHF power converter

The paper proposes a high efficiency RFID UHF power converter unit to overcome the low efficiency problem. This power converter is mainly composed of an RF-DC converter and a DC-DC converter. In order to overcome the low efficiency problem in low current consuming condition, a DC-DC converter is added to conventional single RF-DC converter rectifier to increase the rectifying efficiency of the RFDC rectifier. The power converter is implemented in a 0.18 um mixed signal, 1p6m CMOS technology. Simulation shows the power converter has an average improvement of 5% and can achieve efficiency as high as 30% with 900MHz, 16uW RF input power and 1.3 V 3.6uA DC output.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

RFID安全协议的设计与分析

回顾了已有的各种RFID安全机制,重点介绍基于密码技术的RFID安全协议;分析了这些协议的缺陷;讨论了基于可证明安全性理论来设计和分析RFID安全协议的模型和方法.

FET ACTIVE SLOTLINE NOTCH ANTENNAS FOR QUASI-OPTICAL POWER COMBINING

A new active antenna structure with applications in quasi-optical power combining is described. The active antenna combines a slotline FET oscillator with a notch antenna. The new structure was successfully used to create both E-plane and H-plane linear arrays as well as a 2-D array. Preliminary results of radiation patterns and the power combining efficiencies of the arrays are discussed.

A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification(RFID) transponder IC,which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor.The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency.An analytical model of the voltage multiplier,comparison with other charge pumps,simulation results,and chip testing results are presented.

基于RFID的基带通信IP核的设计与仿真

分析基于射频识别(RFID)技术的系统基带通信过程,建立RFID基带传输模型,利用FPGA技术实现具有基带编解码、数据收发功能的通信IP核,介绍基于模块化思想的基带通信IP核的RTL设计方法,利用QuartusⅡ与Simulink工具进行系统仿真,仿真实验结果表明,该通信模块是有效的,能够为设计RFID通信系统提供高度集成的基带通信IP核。

RFID系统优化模型与智能算法研究

射频识别技术（Radio Frequency Identification, RFID）作为采集与处理信息的高新技术和信息化标准的基础，被列为本世纪十大重要技术之一。但是，RFID技术的大规模实际应用仍处于探索阶段，RFID系统的应用基础技术还存在着大量尚未解决的关键问题，其中RFID系统优化是RFID技术研究和应用的重要课题。由于RFID系统本身的动态性和不确定性， RFID系统优化面对的一般是非线性、多目标、大规模的复杂优化问题，传统的数学优化算法在处理这些问题时，存在困难。为此，研究新的优化算法成为RFID技术实际应用和理论研究中必须解决的课题。 智能计算方法是求解复杂RFID系统优化问题的一种可供选择的算法。智能计算作为一个新兴领域，其发展已引起了多个学科领域研究人员的关注，目前已经成为人工智能、经济、社会、生物等交叉学科的研究热点和前沿领域。智能计算的各类算法已在传统NP问题求解及诸多实际应用领域中展现出其优异的性能和巨大的发展潜力。 本文旨在对RFID系统的各种优化问题进行深入研究和探讨，面向RFID技术的实际应用需求构建其优化模型，并基于智能计算思想设计能够有效求解这些复杂模型的新型智能优化算法。具体研究内容包括： 首先，进行了RFID读写器网络的调度问题研究。在深入分析RFID网络中读写器冲突类型和成因的基础上，考虑RFID网络中的读写器冲突约束，以最小化系统中的频道数量、时隙分配以及总处理时间建立了RFID读写器网络调度的数学优化模型。从生物学的角度出发提出基于生态捕食模型的改进PSO算法（Particle Swarm Optimizer based on Predator-prey Coevolution, PSOPC），在一定程度上解决了PSO算法在迭代后期随着多样性丧失而陷入局部最优的缺点。应用PSOPC设计了求解RFID读写器网络调度模型的智能求解算法，分别给出算法的求解框架、关键步骤的实现机制。通过在不同规模的RFID读写器网络上进行实例仿真，验证了算法的有效性和模型的正确性。 其次，进行了基于菌群自适应觅食算法RFID网络规划问题的研究。考虑RFID系统在不同应用环境下的系统需求，建立了RFID网络规化的数学模型，其目标函数分别为：RFID网络标签覆盖率的最大化目标函数、RFID读写器冲突的最小化目标函数、RFID网络运行的经济效益最大化目标函数、RFID网络运行的负载平衡目标函数以及同时考虑全局目标的混合目标函数。将自然界生物觅食所采用的自适应搜索策略与细菌的趋化行为和群体感应机制相集成，提出了适合求解复杂RFID网络规划问题的菌群自适应觅食算法（Adaptive Bacterial Foraging Optimization, ABFO）。通过仿真实验基于ABFO算法分别对RFID网络规划模型中的五个目标函数进行了实例求解和分析，测试结果与标准PSO算法和遗传算法进行了比较分析。 再次，进行了基于系统智能方法的RFID网络规划分布式决策模型研究。采用分布式决策的思想建立了RFID网络规划的层次模型，在一定程度上缓解、分散了RFID网络规划问题的复杂性，以解决具有混合变量（包括离散变量和连续变量）的多目标RFID网络规划问题。针对层次模型求解的复杂性，以复杂适应系统理论为指导思想设计了一种新型系统智能优化算法对RFID网络规划的层次模型进行求解。系统智能算法将群体智能中的单层群体系统概念扩展为多层涌现系统，仿真实验表明新提出的算法显著提高了智能计算方法的寻优能力，以及算法的适应性、鲁棒性和平衡性等性能。 最后，进行了RFID网络目标跟踪系统中的数据融合研究。以基于RFID技术的目标定位与跟踪系统为应用背景，提出了基于模糊聚类方法的多RFID读写器数据融合模型框架。通过深入分析蜜蜂采蜜的基本生物学规律，对蜜蜂的个体行为及群体行为进行模拟，提出了一类新型群体智能优化算法-蜂群优化算法（Bee Swarm Optimization, BSO），并将BSO算法嵌入RFID目标定位跟踪系统，作为其模糊聚类的基本算法。仿真研究表明，提出的融合模型能够有效的过滤读写器对跟踪目标的错误监测数据，显著提高目标定位与跟踪的精度。