35 resultados para 312.23

em Chinese Academy of Sciences Institutional Repositories Grid Portal


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<正> 本项成果,是承包美国太阳东方勘探公司任务而完成的。在系统分析总结了南海西部石油公司“南海—503工程地质取芯船”在南海北部湾23/25太阳区块所进行的测深、侧扫声纳、地震声学剖面测量,及4口孔深40米的工程地质浅钻土柱等材料的基础上,详细阐述了

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We have developed a two-stage Ti:sapphire amplifier system which can produce 17-TW/23-fs pulses at a repetition rate 10 MHz. A birefringent plate is used in the regenerative amplifier to alleviate gain narrowing, while an all-reflective cylindrical-mirror-based pulse stretcher and an acousto-optic programmable dispersive filter (AOPDF) are used to compensate for the higher order dispersion of the system.

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Przewalskin A (1), a novel C-23 terpenoid with a 6/6/7 carbon ring skeleton, was isolated from Salvia przewalskii. Its structure was determined by comprehensive 1D NMR, 2D NMR, and MS spectroscopic analysis and subsequently confirmed by a single-crystal X

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为探讨利用太阳光降解水中异味化合物的可行性,对2-甲基异莰醇(MIB)、β-柠檬醛(β-Cyclocitral)和β-紫罗兰酮(β-Ionone)等3种异味化合物在紫外光和太阳光下的光降解及光催化降解效果进行了研究。结果表明,单波长紫外光——UVC(254 nm)和UVB(312 nm)及太阳光均能有效降解纯水中的β-Cyclocitral和β-Ionone,但不能降解MIB。加入纳米TiO2后,在UVC(254 nm)、UVB(312 nm)和太阳光照射下,MIB、β-Cyclocitral和β-Ion

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分析了分布于青藏高原及其邻近地区23个种和亚种36个群体高度特化等级裂腹鱼类的线粒体DNA细胞色素b序列,重建了系统发育关系.并采用地质隔离事件校正分支时间,估计了主要分支发生时间.结果发现,高度特化等级裂腹鱼类不是单系群,裸鲤属和裸裂尻属也不是单系群.全裸重唇鱼可能是特化类群向高度特化类群演化的过渡类型.高度特化等级裂腹鱼类的系统发育关系总体上反映了水系之间和地质历史的联系,即来自相同和相邻水系的物种通常具有更近的亲缘关系.估计的主要分支发生事件与青藏高原近晚地质时期强烈隆起有很好的一致性,表明高度特化

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于2010-11-23批量导入

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With the development of LSI, FPGA/CPLD has been used more and more in the fields of digital signal processing and au-tocontrol and so on. And with the development of the techniques of digital processing, for fitting the system’s function, it should be a higher requirement to speed and used-resource to compute the floating point numbers. The author introduces a high speed adder-subtracter of the 23 bit’s floating point numbers, which is carried out with the parallel arithmetic and the computational speed cou...中文文摘:随着大规模集成电路的不断发展,FPGA/CPLD在数字信号处理、自动控制等方面得到了越来越多的应用。并且伴随着数字化处理技术的不断发展,为满足系统功能的要求,对浮点数运算的速度以及相应占用的资源也就提出了更高的要求。笔者即介绍了以VHDL语言为基础,采用并行算法且计算速度达到33MHz的,对23位标准浮点数实现的高速浮点加减法运算器,并以Cyclone II芯片EP2C20F484为硬件环境,最终进行时序模拟仿真,从而验证该浮点加减法器的正确性和快速特性。