An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-mu m CMOS technology, and measures 1.47 mm X 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.

A low power integrated CMOS transmitter for BCI system

The prototype wafer of a low power integrated CMOS Transmitter for short-range biotelemetry application has been designed and fabricated, which is prospective to be implanted in the human brain to transfer the extracted neural information to the external computer. The transmitter consists of five parts, a bandgap current regulator, a ring oscillator, a buffer, a modulator and a power transistor. High integration and low power are the most distinct criteria for such an implantable integrated circuit. The post-simulation results show that under a 3.3 V power supply the transmitter provides 100.1 MHz half-wave sinusoid current signal to drive the off-chip antenna, the output peak current range is -0.155 mA similar to 1.250 mA, and on-chip static power dissipation is low to 0.374 mW. All the performances of the transmitter satisfy the demands of wireless real-time BCI system for neural signals recording and processing.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.

A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver

A DC-offset cancellation scheme in the 5GHz direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard is described in this paper. It uses the analog feedback loop to eliminate the DC-offset at the output of the double-balanced mixer. The mixer has a simulation voltage conversion gain of IMB at 5.2GHz, noise figure of 9.67dB, IIP3 of 7.6dBm. The solution provides 39.1dB reduction according to the leakage value at LO and mixer load resistors, the additional noise figure added to mixer is less than 0.9dB, the added power dissipation is 0.1mW and was fabricated in 60GHz 0.35 mu m SiGe BiCMOS technology.

A novel low-power input-independent MOS AC/DC charge pump

This paper presents a novel fully integrated MOS AC to DC charge pump with low power dissipation and stable output for RFID applications. To improve the input sensitivity, we replaced Schottky-diodes in conventional charge pumps with MOS diodes with zero threshold, which has less process defects and is thus more compatible with other circuits. The charge pump in a RFID transponder is implemented in a 0.35um CMOS technology with 0.24 sq mm die size. The analytical model of the charge pump and the simulation results are presented.

Room temperature operation of photonic-crystal distributed-feedback quantum cascade lasers with single longitudinal and lateral mode performance

We demonstrate room temperature operation of photonic-crystal distributed-feedback quantum cascade lasers emitting at 4.7 mu m. A rectangular photonic crystal lattice perpendicular to the cleaved facet was defined using holographic lithography. The anticrossing of the index- and Bragg-guided dispersions of rectangular lattice forms the band-edge mode with extended mode volume and reduced group velocity. Utilizing this coupling mechanism, single mode operation with a near-diffractive-limited divergence angle of 12 degrees is obtained for 33 mu m wide devices in a temperature range of 85-300 K. The reduced threshold current densities and improved heat dissipation management contribute to the realization of devices' room temperature operation.

Thermal induced facet destructive feature of quantum cascade lasers

We present a study on the facet damage profile of quantum cascade lasers (QCLs). Conspicuous cascade half-loop damage strips on front facet are observed when QCLs catastrophically failed. Due to the large difference on thermal conductivities between active region and the substrate, dominant heat is compulsively driven to the substrate. Abundant heat accumulation and dissipation on substrate build large temperature gradient and thermal lattice mismatch. Thermal-induced stress due to sequential mismatch leads to the occurrence of the multistep damages on front facet. Good agreement is achieved between the observed locations of damaged strips and the calculated results.

Numerical simulations of interrupted and conventional microchannel heat sinks

We provide three-dimensional numerical simulations of conjugate heat transfer in conventional and the newly proposed interrupted microchannel heat sinks. The new microchannel heat sink consists of a set of separated zones adjoining shortened parallel microchannels and transverse microchambers. Multi-channel effect, physical property variations, and axial thermal conduction are considered. It is found that flow rate variations in different channels can be neglected, while heat received by different channels accounts for 2% deviations from the averaged value when the heat flux at the back surface of the silicon chip reaches 100 W/cm(2). The computed hydraulic and thermal boundary layers are redeveloping in each separated zone due to shortened flow length for the interrupted microchannel heat sink. The periodic thermal developing flow is responsible for the significant heat transfer enhancement. Two effects influence pressure drops across the newly proposed microchannel heat sink. The first one is the pressure recovery effect in the microchamber, while the second one is the head loss when liquid leaves the microchamber and enters the next zone. The first effect compensates or suppresses the second one, leading to similar or decreased pressure drop than that for the conventional microchannel heat sink, with the fluid Prandtl number larger than unity.

黄土高原半干旱区侧柏(Platycladus orientalis)树干液流动态

应用热扩散式树干茎流计(TDP)于2008年4～10月对黄土高原安塞县侧柏人工林树干液流速率进行了连续测定,并对周围气象、土壤水分等多个环境因子进行了同步测定。结果表明:侧柏在不同月份晴天树干液流速率变化具有明显的昼夜节律性,呈单峰曲线;且各月液流速率日均值受土壤供水水平限制总体上呈下降趋势,即4月份最大,为0.00135cm.s-1;10月份最小为0.00011cm.s-1;树干液流速率与光合有效辐射、大气温度、水汽压差呈极显著正相关,与相对湿度呈负相关,其相关程度:光合有效辐射>水汽压差>大气温度>相对湿度,并可用线性表达式来估算;侧柏边材面积和地径呈幂指数关系,并以此结合密度估算出样地侧柏人工林的边材面积为4.65m2,最终估算出侧柏人工林生长季总耗水量为1159.6t.hm-2。

乔木蒸腾耗水量研究方法述评与展望

参阅了大量国内外有关乔木蒸腾研究方法文献,认为乔木蒸腾量研究方法主要有二大类,即组织器官测定、单木测定;分类对典型研究方法(快速称重法、气孔计法、整株容器称重法、同位素示踪法、热脉冲法、树干热平衡法、热扩散探针法)进行了述评,对比分析了各种方法间的优缺点及其适用范围;展望了乔木蒸腾耗水作用研究方法的应用前景,认为热技术法是未来几年内的主要测定方法。

黄土高原半干旱区人工林刺槐展叶期树干液流动态分析

应用热扩散式树干茎流计(TDP)于2008年4月26日至5月31日,在黄土高原半干旱区安塞县对人工林刺槐展叶期树干液流及其气象、土壤水分等6个指标进行连续测定。结果表明:刺槐展叶期可分为芽期、展叶初期、中期和全叶期。在芽期,刺槐树干液流速率日变化无明显昼夜波动;在展叶初期至全叶期日变化呈现出从微弱波动逐渐增大到趋于平稳的剧烈波动;在展叶中期以后液流速率表现为上升快、下降缓慢的单峰曲线;在全叶期平均峰值约为0.0027cm.s-1;树干液流速率与光合有效辐射强度、大气温度、水蒸气压亏缺和风速呈极显著正相关,与相对湿度呈负相关,其相关程度依次为光合有效辐射强度>大气温度>水蒸气压亏缺>相对湿度>风速,且可用光合有效辐射强度和大气温度线性表达式来估测;土壤水分在展叶期呈逐渐减少趋势,但对树干液流的胁迫不显著;在展叶期刺槐单株日蒸腾耗水量随直径的增大而增大并与胸径呈良好的线性关系,可用来估算展叶期刺槐人工林蒸腾耗水量。

A novel noise optimization technique for inductively degenerated CMOS LNA

This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

A multi-standard active-RC filter with accurate tuning system

A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architec-ture is presented. It exhibits 1EEE 802. 11a/b/g (9.5 MHz) and DVB-H (3 MHz, 4 MHz) application. The filter exploits digitally-controlled polysilicon resistor banks and a phase lock loop type automatic tuning system. The novel and complex automatic frequency calibration scheme provides better than 4 comer frequency accuracy, and it can be powered down after calibration to save power and avoid digital signal interference. The filter achieves OIP3 of 26 dBm and the measured group delay variation of the receiver filter is 50 ns (WLAN mode). Its dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from a 2.85 V supply. The dissipation of calibration consumes 2 mA. The circuit has been fabricated in a 0.35μm 47 GHz SiGe BiCMOS technology; the receiver and transmitter filter occupy 0.21 mm~2 and 0.11 mm~2 (calibration circuit excluded), respectively.

A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node

This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.

A Hybrid Random Number Generator Using Single Electron Tunneling Junctions and MOS Transistors

This paper proposes a novel single electron random number generator (RNG). The generator consists of multiple tunneling junctions (MTJ) and a hybrid single electron transistor (SET)/MOS output circuit. It is an oscillator-based RNG. MTJ is used to implement a high-frequency oscillator,which uses the inherent physical randomness in tunneling events of the MTJ to achieve large frequency drift. The hybrid SET and MOS output circuit is used to amplify and buffer the output signal of the MTJ oscillator. The RNG circuit generates high-quality random digital sequences with a simple structure. The operation speed of this circuit is as high as 1GHz. The circuit also has good driven capability and low power dissipation. This novel random number generator is a promising device for future cryptographic systems and communication applications.