Nonadiabatic geometric quantum computation with trapped ions

We propose a nonadiabatic scheme for geometric quantum computation with trapped ions. By making use of the Aharonov-Anandan phase, the proposed scheme not only preserves the globally geometric nature in quantum computation, but also provides the advantage of nonadiabaticity that overcomes the problem of slow evolution in the existing adiabatic schemes. Moreover, the present scheme requires only two atomic levels in each ion, making it an appealing candidate for quantum computation.

Quantum computation with coupled quantum dots embedded in optical microcavities

Based on an idea that spatial separation of charge states can enhance quantum coherence, we propose a scheme for a quantum computation with the quantum bit (qubit) constructed from two coupled quantum dots. Quantum information is stored in the electron-hole pair state with the electron and hole located in different dots, which enables the qubit state to be very long-lived. Universal quantum gates involving any pair of qubits are realized by coupling the quantum dots through the cavity photon which is a hopeful candidate for the transfer of long-range information. The operation analysis is carried out by estimating the gate time versus the decoherence time.

Analog computation using quantum-dot cell network

A novel analog-computation system using a quantum-dot cell network is proposed to solve complex problems. Analog computation is a promising method for solving a mathematical problem by using a physical system analogous to the problem. We designed a novel quantum-dot cell consisting of three-stacked. quantum dots and constructed a cell network utilizing the nearest-neighbor interactions between the cells. We then mapped a graph 3-colorability problem onto the network so that the single-electron configuration of the network in the ground state corresponded to one of the solutions. We calculated the ground state of the cell network and found solutions to the problems. The results demonstrate that analog computation is a promising approach for solving complex problems.

Computation of resonant frequencies and quality factors of cavities by FDTD technique and Pade approximation

The finite-difference time domain (FDTD) technique and the Pade approximation with Baker's algorithm are used to calculate the mode frequencies and quality factors of cavities. Comparing with the fast Fourier transformation/Pade method, we find that the Fade approximation and the Baker's algorithm can obtain exact resonant frequencies and quality factors based on a much shorter time record of the FDTD output.

Parallel optical communication subsystem based on VCSEL - art. no. 67833I

A parallel optical communication subsystem based on a 12 channels parallel optical transmitter module and a 12 channels parallel optical receiver module can be used as a 10Gbps STM-64 or an OC-192 optical transponder. The bit error rate of this parallel optical communication subsystem is about 0 under the test by SDH optical transport tester during three hours and eighteen minutes.

The application of parallel optical transmitter and receiver modules in communication subsystems

A new 12 channels parallel optical transmitter module in which a Vertical Cavity Surface Emitting Laser (VCSEL) has been selected as the optical source is capable of transmitting 37.5Gbps date over hundreds meters. A new 12 channels parallel optical receiver module in which a GaAs PIN (p-intrinsic-n-type) array has been selected as the optical receiver unit is capable of responding to 30Gbps date. A transmission system based on a 12 channels parallel optical transmitter module and a 12 channels parallel optical receiver module can be used as a 10Gbps STM-64 or an OC-192 optical transponder. The parallel optical modules and the parallel optical transmission system have passed the test in laboratory.

VCSEL-based parallel optical transmission module

This paper describes the design process and performance of the optimized parallel optical transmission module. Based on 1x12 VCSEL (Vertical Cavity Surface Emitting Laser) array, we designed and fabricated the high speed parallel optical modules. Our parallel optical module contains a 1x12 VCSEL array, a 12 channel CMOS laser driver circuit, a high speed PCB (Printed Circuit Board), a MT fiber connector and a packaging housing. The L-I-V characteristics of the 850nm VCSEL was measured at the operating current 8mA, 3dB frequency bandwidth more than 3GHz and the optical output 1mW. The transmission rate of all 12 channels is 30Gbit/s, with a single channel 2.5Gbit/s. By adopting the integration of the 1x12 VCSEL array and the driver array, we make a high speed PCB (Printed Circuit Board) to provide the optoelectronic chip with the operating voltage and high speed signals current. The LVDS (Low-Voltage Differential Signals) was set as the input signal to achieve better high frequency performance. The active coupling was adopted with a MT connector (8 degrees slant fiber array). We used the Small Form Factor Pluggable (SFP) packaging. With the edge connector, the module could be inserted into the system dispense with bonding process.

Proposed scheme for parallel 10Gb/s VSR system and its Verilog HDL realization

This paper proposes a novel and innovative scheme for 10Gb/s parallel Very Short Reach (VSR) optical communication system. The optimized scheme properly manages the SDH/SONET redundant bytes and adjusts the position of error detecting bytes and error correction bytes. Compared with the OIF-VSR4-01.0 proposal, the scheme has a coding process module. The SDH/SONET frames in transmission direction are disposed as follows: (1) The Framer-Serdes Interface (FSI) gets 16x622.08Mb/s STM-64 frame. (2) The STM-64 frame is byte-wise stripped across 12 channels, all channels are data channels. During this process, the parity bytes and CRC bytes are generated in the similar way as OIF-VSR4-01.0 and stored in the code process module. (3) The code process module will regularly convey the additional parity bytes and CRC bytes to all 12 data channels. (4) After the 8B/10B coding, the 12 channels is transmitted to the parallel VCSEL array. The receive process approximately in reverse order of transmission process. By applying this scheme to 10Gb/s VSR system, the frame size in VSR system is reduced from 15552x12 bytes to 14040x12 bytes, the system redundancy is reduced obviously.

有限元单元计算予程序的OpenMP并行化

Intel和AMD双核乃至4核处理器的推出，使得并行计算已经普及到PC机。为了充分利用多核，需要对原有程序进行多线程改造，使其充分利用多核处理带来的性能提升。该文利用共享存储编程的工业标准OpenMP对有限元方法涉及的单元计算子程序进行了并行化实现。在机群的一个双CPU的SMP节点上的测试表明，共享并行化使得该单元子程序的性能提高了一倍。