Superluminal radio source PKS 0420-014

The very long baseline interferometry result of a superluminal radio source PKS 0420-014 at 5 GHz with Shanghai (China), Urumqi (China), Note (Italy), and HartRAO (South Africa) telescopes is presented. Proper motions of the relativistic jet components in the source are calculated. Based on the Self-Compton emission in a uniform spherical model, the beaming parameters of the source are estimated. The results show that PKS 0420-014 has a high Doppler factor of 9.3, a Lorentz factor of 6.5, and a small angle of 5.5 degrees to the line of sight.

The radio counter-jet of the QSO 3C 48

We present multi- frequency radio observational results of the quasar 3C 48. The observations were carried out with the Very Large Array ( VLA) at five frequencies, 0.33, 1.5, 4.8, 8.4, and 22.5 GHz, and with the Multi- Element Radio Linked Interferometer Network ( MERLIN) at the two frequencies of 1.6 and 5 GHz. The source shows a one- sided jet to the north within 1", which then extends to the northeast and becomes diffuse. Two bright components ( N2 and N3), containing most of the flux density, are present in the northern jet. The spectral index of the two components is alpha(N2) similar to -0.99 +/- 0.12 and alpha(N3) similar to - 0.84 +/- 0.23 ( S proportional to nu(alpha)). Our images show the presence of an extended structure surrounding component N2, suggestive of strong interaction between the jet and the interstellar medium ( ISM) of the host galaxy. A steep- spectrum component, labelled S, located 0.25 " southwest to the flat- spectrum component which could be the core of 3C 48, is detected at a significance of > 15 sigma. Both the location and the steepness of the spectrum of component S suggest the presence of a counter- jet in 3C 48.

针对一种多模式逻辑单元结构FPGA的工艺映射

结合FPGA设计的特点,提出一种可灵活配置的多模式FPGA逻辑单元结构及对其进行工艺映射的工具VMAP.该工具中除了采用一般的工艺映射算法外,还结合逻辑单元结构特点提出了专门的合并优化算法.该算法基于图的最大基数匹配,将部分查找表进行合并,减小了映射结果的面积开销.实验结果表明.对于标准的测试电路,结合文中的逻辑单元结构和合并算法得到的工艺映射结果平均可以减少15.7%的基本逻辑单元使用个数.

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

FPGA中专用可重构乘法器的设计

提出了一种新的嵌入在FPGA中可重构的流水线乘法器设计.该设计采用了改进的波茨编码算法,可以实现18×18有符号乘法或17×17无符号乘法.还提出了一种新的电路优化方法来减少部分积的数目,并且提出了一种新的乘法器版图布局,以便适应tilebased FPGA芯片设计所加的约束.该乘法器可以配置成同步或异步模式,也町以配置成带流水线的模式以满足高频操作.该设计很容易扩展成不同的输入和输出位宽.同时提出了一种新的超前进位加法器电路来产生最后的结果.采用了传输门逻辑来实现整个乘法器.乘法器采用了中芯国际0.13μm CMOS工艺来实现,完成18×18的乘法操作需要4.1ns.全部使用2级的流水线时,时钟周期可以达到2.5ns.这比商用乘法器快29.1%,比其他乘法器快17.5%.与传统的基于查找表的乘法器相比,该乘法器的面积为传统乘法器面积的1/32.

一种灵活的包含嵌入式存储器的FPGA结构

近年来,集成电路制造工艺的巨大提高使得FPGA有能力实现大的数字系统电路。这些大的系统通常需要大量的存储器以存储数据。很多FPGA生产商已经推出了含有大的嵌入式存储器的FPGA芯片。然而,大多数学术方面的CAD工具只针对于同质的FPGA结构(即只包括逻辑模块和布线通道的FPGA结构)。FPGA的布线结构通常被表示为RRG(布线资源图)。本文将介绍一种包含嵌入式存储器模块的FPGA的灵活结构以及一种建立RRG的方法。文中我们对VPR(versatile placing and routing)进行了改进,使得VPR可以处理包含嵌入式存储器结构的FPGA的布局布线问题,同时保持了VPR的灵活性。

平台式FPGA中可重构存储器模块的设计

可重构静态存储器(SRAM)模块是场可编程门阵列(FPGA)的重要组成部分,它必须尽量满足用户不同的需要,所以要有良好的可重构性能.本文设计了一款深亚微米工艺下的16-kb的高速,低功耗双端口可重构SRAM.它可以重构成16Kx1,8Kx2,4Kx4,2Kx8,1Kx16和512x32六种不同的工作模式.基于不同的配置选择,此SRAM可以配置为双端口SRAM,单端口SRAM,ROM,FIFO,大的查找表或移位寄存器,本文完整介绍了该SRAM的设计方法,重点介绍了一种新颖的存储单元电路结构:三端口存储单元,以及用于实现可重构功能的电路的设计方法.