100 resultados para z-scan
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AlGaN/AlN/GaN high electron mobility transistor (HEMT) structures with high mobility GaN channel layer were grown on 50 min diameter semi-insulating (SI) 6H-SiC substrates by metalorganic chemical vapor deposition and large periphery HEMT devices were fabricated and characterized. High two-dimensional electron gas mobility of 2215 cm(2)/V s at room temperature with sheet electron concentration of 1.044 x 10(13)/cm(2) was achieved. The 50 mm diameter HEMT wafer exhibited a low average sheet resistance of 251.0 Omega/square, with the resistance uniformity of 2.02%. Atomic force microscopy measurements revealed a smooth AlGaN surface with a root-mean-square roughness of 0.27 nm for a scan area of 5 mu mi x 5 pm. The 1-mm gate width devices fabricated using the materials demonstrated a very high continuous wave output power of 9.39 W at 8 GHz, with a power added efficiency of 46.2% and power gain of 7.54 dB. A maximum drain current density of 1300 mA/mm, an extrinsic transconductance of 382 mS/mm, a current gain cutoff frequency of 31 GHz and a maximum frequency of oscillation 60 GHz were also achieved in the same devices. (C) 2007 Elsevier Ltd. All rights reserved.
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IEEE Computer Society
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采用射频磁控反应溅射技术与热退火处理制备了nc-Si/SiN_x多量子阱材料.对样品进行了小角度XRD、Raman光谱、吸收光谱测试,研究了其结构和光学性质.采用皮秒脉冲激光单光束Z-扫描技术研究了样品在非共振吸收区的三阶非线性光学特性.实验结果表明,其非线性折射率为负值,非线性吸收属于双光子吸收.由实验数据计算得材料三阶非线性极化率为7.50×10~(-8)esu,该值比体硅材料的三阶非线性极化率大4个数量级.对材料光学非线性产生的机理进行了探讨,认为材料的非线性极化率的增加来源于材料量子限制效应增强.
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The principle of step-scan Fourier transform infrared (FTIR) spectroscopy is introduced. Double modulation step-scan FTIR technique is used to obtain the quantum cascade laser's stacked emission spectra in the time domain. Optical property and thermal accumulation of devices due to large drive current are analyzed.
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国家自然科学基金
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于2010-11-23批量导入
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一种多步生长方法应用于GaAs衬底上的In_xGa_(1-x)As缓冲层的MOCVD生长.在这种In_xGa_(1-x)As缓冲层上生长的In_yGa_(1-y)As/Al_zGa_(1-z)As/GaAs/Al_zGa_(1-x)As双垫垒量子阱材料表现出了很好的晶格特性和光学性质.超晶格的室温光伏谱中出现很强的22H高阶机制吸收峰,表明超晶格界面质量很好.主要应用X射线双晶衍射方法,给出了样品中各层的应变状态.据此,合理地解释了样品的光学测试结果.
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Scan test can be inserted around hard IP cores that have not been designed with DFT approaches. An 18x18 bits Booth Coding-Wallace Tree multiplier has been designed with full custom approach with 0.61 m CMOS technology. When we reuse the multiplier in another chip, scan chain has been inserted around it to increase the fault coverage. After scan insertion, the multiplier needs 4.7% more areas and 24.4% more delay time, while the fault coverage reaches to 95%.