Comparative studies on parallel and antiparallel duplex and triplex DNA

Parallel strand models for base sequences d(A)(10). d(T)(10), d(AT)(5) . d(TA)(5), d(G(5)C(5)). d(C(5)G(5)), d(GC)(5) . d(CG)(5) and d(CTATAGGGAT). d(GATATCCCTA), where reverse Watson-Crick A-T pairing with two H-bonds and reverse Watson-Crick G-C pairing with one H-bond or with two H-bonds were adopted, and three models of d(T)(14). d(A)(14). d(T)(14) triple helix with different strand orientations were built up by molecular architecture and energy minimization. Comparisons of parallel duplex models with their corresponding B-DNA models and comparisons among the three triple helices showed: (i) conformational energies of parallel AT duplex models were a little lower, while for GC duplex models they were about 8% higher than that of their corresponding B-DNA models; (ii) the energy differences between parallel and B-type duplex models and among the three triple helices arose mainly from base stacking energies, especially for GC base pairing; (iii) the parallel duplexes with one H-bond G-C pairs were less stable than those with two H-bonds G-C pairs. The present paper includes a brief discussion about the effect of base stacking and base sequences on DNA conformations. (C) 1997 Academic Press Limited.

A programmable SIMD vision chip for real-time vision applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 x 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 x 16 PE array is fabricated by the 0.18 mu m standard CMOS process. It has a pixel size of 30 mu m x 40 mu m and 8.72 mW power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.

1 x 4 Ge-on-SOI PIN Photodetector Array for Parallel Optical Interconnects

High-quality Ge film was epitaxially grown on silicon on insulator using the ultrahigh vacuum chemical vapor deposition. In this paper, we demonstrated that the efficient 1 4 germanium-on-silicon p-i-n photodetector arrays with 1.0 mu m Ge film had a responsivity as high as 0.65 A/W at 1.31 mu m and 0.32 A/W at 1.55 mu m, respectively. The dark current density was about 0.75 mA/cm(2) at 0 V and 13.9 mA/cm(2) at 1.0 V reverse bias. The detectors with a diameter of 25 mu m were measured at 1550 nm incident light under 0 V bias, and the result showed that the 3-dB bandwidth is 2.48 GHz. At a reverse bias of 3 V, the bandwidth is about 13.3 GHz. The four devices showed a good consistency.

Magnetic field switching in parallel quantum dots

We show that the Coulomb blockade in parallel dots pierced by magnetic flux Phi completely blocks the resonant current for any value of Phi except for integer multiples of the flux quantum Phi(0). This non-analytic (switching) dependence of the current on Phi arises only when the dot states that carry the current are of the same energy. The time needed to reach the steady state, however, diverges when Phi -> n Phi(0). Copyright (C) EPLA, 2009

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

Optical microwave generation using two parallel DFB lasers integrated with Y-branch waveguide coupler

A new device of two parallel distributed feedback (DFB) lasers integrated monolithically with Y-branch waveguide coupler was fabricated by means of quantum well intermixing. Optical microwave signal was generated in the Y-branch waveguide coupler through frequency beating of the two laser modes coming from two DFB laser in parallel, which had a small difference in frequency. Continuous rapid tuning of optical microwave signal from 13 to 42 GHz were realized by adjusting independently the driving currents injected into the two DFB lasers.

Optical properties of semiconductor quantum-well material using photonic crystal fabricated by micro-fabrication machine

Two-dimensional photonic crystals in near infrared region were fabricated by using the focused ion beam ( FIB) method and the method of electron-beam lithography (EBL) combined with dry etching. Both methods can fabricate perfect crystals, the method of FIB is simple,the other is more complicated. It is shown that the material with the photonic crystal fabricated by FIB has no fluorescence,on the other hand, the small-lattice photonic crystal made by EBL combined with dry etching can enhance the extraction efficiency two folds, though the photonic crystal has some disorder. The mechanisms of the enhanced-emission and the absence of emission are also discussed.

Interdot interaction induced zero-bias maximum of the differential conductance in parallel double quantum dots

We have studied the equilibrium and nonequilibrium electronic transports through a double quantum dot coupled to leads in a symmetrical parallel configuration in the presence of both the inter- and the intradot Coulomb interactions. The influences of the interdot interaction and the difference between dot levels on the local density of states (LDOS) and the differential conductance are paid special attention. We find an interesting zero-bias maximum of the differential conductance induced by the interdot interaction, which can be interpreted in terms of the LDOS of the two dots. Due to the presence of the interdot interaction, the LDOS peaks around the dot levels epsilon(i) are split, and as a result, the most active energy level which supports the transport is shifted near to the Fermi level of the leads in the equilibrium situation. (c) 2006 American Institute of Physics.

Determination of the absorption for incident light propagating parallel through the guest-host polymer film waveguide

Guest host polymer thin films of polymethyl methacrylate (PMMA) incorporated with (4'-nitrobenzene)-3-azo-9-ethylcarbazole (NAEC) were fabricated by spin coating and then poled by the method of corona-onset poling at elevated temperature. The absorption mechanism of the polymeric film, which is very important for the optical transmission losses and directly relates to the orientation of chromophore NAEC in polymer PMMA, was investigated in detail. From the UV-visible absorption spectra for NAEC/PMMA film before and after being poled, we determined the change of absorption coefficient kappa with the wavelength and approximately calculated the maximum absorption A(parallel tomax) as 3.46 for incident light propagating parallel through the film, i.e. the ordinary polarized light, which cannot be directly measured in the spectro photometer. (C) 2002 Elsevier Science Ltd. All rights reserved.

Parallel optical communication subsystem based on VCSEL - art. no. 67833I

A parallel optical communication subsystem based on a 12 channels parallel optical transmitter module and a 12 channels parallel optical receiver module can be used as a 10Gbps STM-64 or an OC-192 optical transponder. The bit error rate of this parallel optical communication subsystem is about 0 under the test by SDH optical transport tester during three hours and eighteen minutes.

The application of parallel optical transmitter and receiver modules in communication subsystems

A new 12 channels parallel optical transmitter module in which a Vertical Cavity Surface Emitting Laser (VCSEL) has been selected as the optical source is capable of transmitting 37.5Gbps date over hundreds meters. A new 12 channels parallel optical receiver module in which a GaAs PIN (p-intrinsic-n-type) array has been selected as the optical receiver unit is capable of responding to 30Gbps date. A transmission system based on a 12 channels parallel optical transmitter module and a 12 channels parallel optical receiver module can be used as a 10Gbps STM-64 or an OC-192 optical transponder. The parallel optical modules and the parallel optical transmission system have passed the test in laboratory.

VCSEL-based parallel optical transmission module

This paper describes the design process and performance of the optimized parallel optical transmission module. Based on 1x12 VCSEL (Vertical Cavity Surface Emitting Laser) array, we designed and fabricated the high speed parallel optical modules. Our parallel optical module contains a 1x12 VCSEL array, a 12 channel CMOS laser driver circuit, a high speed PCB (Printed Circuit Board), a MT fiber connector and a packaging housing. The L-I-V characteristics of the 850nm VCSEL was measured at the operating current 8mA, 3dB frequency bandwidth more than 3GHz and the optical output 1mW. The transmission rate of all 12 channels is 30Gbit/s, with a single channel 2.5Gbit/s. By adopting the integration of the 1x12 VCSEL array and the driver array, we make a high speed PCB (Printed Circuit Board) to provide the optoelectronic chip with the operating voltage and high speed signals current. The LVDS (Low-Voltage Differential Signals) was set as the input signal to achieve better high frequency performance. The active coupling was adopted with a MT connector (8 degrees slant fiber array). We used the Small Form Factor Pluggable (SFP) packaging. With the edge connector, the module could be inserted into the system dispense with bonding process.

Proposed scheme for parallel 10Gb/s VSR system and its Verilog HDL realization

This paper proposes a novel and innovative scheme for 10Gb/s parallel Very Short Reach (VSR) optical communication system. The optimized scheme properly manages the SDH/SONET redundant bytes and adjusts the position of error detecting bytes and error correction bytes. Compared with the OIF-VSR4-01.0 proposal, the scheme has a coding process module. The SDH/SONET frames in transmission direction are disposed as follows: (1) The Framer-Serdes Interface (FSI) gets 16x622.08Mb/s STM-64 frame. (2) The STM-64 frame is byte-wise stripped across 12 channels, all channels are data channels. During this process, the parity bytes and CRC bytes are generated in the similar way as OIF-VSR4-01.0 and stored in the code process module. (3) The code process module will regularly convey the additional parity bytes and CRC bytes to all 12 data channels. (4) After the 8B/10B coding, the 12 channels is transmitted to the parallel VCSEL array. The receive process approximately in reverse order of transmission process. By applying this scheme to 10Gb/s VSR system, the frame size in VSR system is reduced from 15552x12 bytes to 14040x12 bytes, the system redundancy is reduced obviously.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.