66 resultados para Digital filters


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Metallic gratings with narrow slits can lead to special optical properties such as strongly enhancing the transmission and considerably strengthening the polarized effect. A narrow-band filter suitable for application in optical communication is designed by sandwiching a metallic grating between two identical dielectric films. The maximum transmission can reach 96% after optimizing the parameters of films and grating at a central wavelength of 1053 nm. It is the first time, to our knowledge, that such high transmission has been reported since the discovery of the extraordinarily high transmission through periodic holes or slits; moreover, the extremely polarized effect is also found in P mode of this symmetric grating.

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Simultaneous tone-tone masking in conjunction with the envelope-following response (EFR) recording was used to obtain tuning curves in porpoises Phocoena phocoena and Neophocaena phocaenoides asiaeorientalis. The EFR was evoked by amplitude-modulated probes with a modulation rate of 1000 Hz and carrier frequencies from 22.5 to 140 kHz. Equivalent rectangular quality Q(ERB) of the obtained tuning curves varied from 8.3-8.6 at lower (22.5-32 kHz) probe frequencies to 44.8-47.4 at high (128-140 kHz) frequencies. The QERB dependence on probe frequency could be approximated by regression lines with a slope of 0.83 to 0.86 in log-log scale., which corresponded to almost frequency-proportional quality and almost constant bandwidth of 34 kHz. Thus, the frequency representation in the porpoise auditory system is much closer to a constant-bandwidth rather that to a constant-quality manner. (c) 2006 Acoustical Society of America.

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A detailed study on analyzing the crosstalk in a wavelength division multiplexed fiber laser sensor array system based on a digital phase generated carrier interferometric interrogation scheme is reported. The crosstalk effects induced by the limited optical channel isolation of a dense wavelength division demultiplexer (DWDM) are presented, and the necessary channel isolation to keep the crosstalk negligible to the output signal was calculated via Bessel function expansion and demonstrated by a two serial fiber laser sensors system. Finally, a three-element fiber laser sensor array system with a 50-dB channel-isolation DWDM was built up. Experimental results demonstrated that there was no measurable crosstalk between the output channels.

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This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as-follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than uW; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.

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For a four-port microracetrack channel drop filter, unexpected transmission characteristics due to strong dispersive coupling are demonstrated by the light tunneling between the input-output waveguides and the resonator, where a large dropping transmission at off-resonance wavelengths is observed by finite-difference time-domain simulation. It causes a severe decline of the extinction ratio and finesse. An appropriate decrease of the coupling strength is found to suppress the dispersive coupling and greately increase the extinction ratio and finesse, a decreased coupling strength can be realized by the application of an asymmetrical coupling waveguide structure. In addition, the profile of the coupling dispersion in the transmission spectra can be predicted based on a coupled mode theory analysis of an equivalent system consisting of two coupling straight waveguides. The effects of structure parameters on the transmission spectra obtained by this method agree well with the numerical results. It is useful to avoid the strong dispersive coupling region in the filter design. (c) 2007 Optical Society of America.

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An add-drop filter based on a perfect square resonator can realize a maximum of only 25% power dropping because the confined modes are standing-wave modes. By means of mode coupling between two modes with inverse symmetry properties, a traveling-wave-like filtering response is obtained in a two-dimensional single square cavity filter with cut or circular corners by finite-difference time-domain simulation. The optimized deformation parameters for an add-drop filter can be accurately predicted as the overlapping point of the two coupling modes in an isolated deformed square cavity. More than 80% power dropping can be obtained in a deformed square cavity filter with a side length of 3.01 mu m. The free spectral region is decided by the mode spacing between modes, with the sum of the mode indices differing by 1. (c) 2007 Optical Society of America.

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The authors present the observation of wide transmission dips in a microring channel drop filter by two-dimensional finite-difference time-domain simulation. The authors show that distributed mode coupling between the input waveguide and the resonator results in the oscillations of the coupling efficiency and the envelope of transmission spectra with wavelength. The critical coupling as the light just passing through the coupling region is important for optimizing related devices. If the width of the input waveguide is different from that of the ring resonator, the phenomenon can be greatly reduced. (c) 2006 American Institute of Physics.

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This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

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A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

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A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

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This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

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Wide transmission dips are observed in the through spectra in microring and racetrack channel drop filters by two-dimensional finite-difference time-domain (FDTD) simulation. The transmission spectra, which reflect the coupling efficiency, are also calculated from the FDTD output as the pulse just travels one circle inside the resonator. The results indicate that the dips are caused by the dispersion of the coupling coefficient between the input waveguide and the resonator. In addition, a near-zero channel drop on resonance and a large channel drop off resonance are observed due to the near zero coupling coefficient and a large coupling coefficient, respectively. If the width of the input waveguide is different from that of the ring resonator, the oscillation of the coupling coefficient can be greatly suppressed.

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This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

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Submitted by 阎军 (yanj@red.semi.ac.cn) on 2010-06-04T08:05:17Z No. of bitstreams: 1 High-Order Microring Filters on SOI Wafer.pdf: 236326 bytes, checksum: dea85274da2a205a54b8a46049db9c94 (MD5)