Polarization analysis and experimental implementation of PLZT electro-optical switch using fiber Sagnac interferometers

The polarization characteristics of electro-optical (EO) switches using fiber Sagnac interferometer (FSI) structures are theoretically investigated. Analytical solutions of output fields are presented when the twists and birefringence in a Sagnac loop are considered. Numerical calculations show that the twists of fiber, the orientation of the inserted phase retarder, and the splitting ratio of the coupler will influence both the output intensity and the output polarization properties of the proposed switch. A polarization-independent EO switch based on a Sagnac interferometer and a PUT bar was experimentally implemented, which showed good coincidence with the analytical results. The experiment showed a switch with 22 dB extinction ratio and less than 31.1 ns switching time. (c) 2006 Optical Society of America.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

function definition language fdl and its implementation

A Function Definition Language (FDL) is presented. Though designed for describing specifications, FDL is also a general-purpose functional programming language. It uses context-free language as data type, supports pattern matching definition of functions, offers several function definition forms, and is executable. It is shown that FDL has strong expressiveness, is easy to use and describes algorithms concisely and naturally. An interpreter of FDL is introduced. Experiments and discussion are included.

虚拟硬件方法实现基于Intel StrongARM SA-1110平台的Linux APM

文章讨论了在StrongARM SA－1110开发板上实现Linux APM的主要技术问题。在分析了Intel StrongARM最新处理器SA－1110及开发板（Assabet）与电源管理相关的结构和特性的基础上，提出了一种基于虚拟硬件的系统跨平台移植的方法和思路，并以实际开发过程中的经验为背景，介绍了在Linux APM基于SA－1110平台的移植工作中虚拟硬件方法的应用和虚拟硬件方法在操作系统跨平台移植开发上的优点。

VLSI architecture of a K-best detector for MIMO--OFDM wireless communication systems

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.