A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

An adaptive frequency synthesizer architecture reducing reference sidebands

An adaptive phase-locked loop (PLL) frequency synthesizer architecture for reducing reference sidebands at the output of the frequency synthesizer is described. The architecture combines two tuning loops: one is the main loop for locking the PLL frequency synthesizer and operating all the time, the other one is auxiliary loop for reducing reference sidebands and operating only when the main loop is closely locked. A 1.8V 1GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a 0.18um CMOS process. The suppression of the reference sidebands of the proposed frequency synthesizer is 13.8dB more than that of the general frequency synthesizer.

A Novel 0.72-6.2GHz Continuously-Tunable Delta Sigma Fractional-N Frequency Synthesizer

This paper presents a wideband Delta Sigma-based fractional-N synthesizer with three integrated quadrature VCOs for multiple-input multiple-output (MIMO) wireless communication applications. It continuously covers a wide range frequency from 0.72GHz to 6.2GHz that is suitable for multiple communication standards. The synthesizer is designed in 0.13-um RE CMOS process. The dual clock full differential multi-modulus divide (MMD) with low power consumption can operate over 9GHz under the worst condition. In the whole range frequency from 0.72GHz to 6.2GHz, the maximal tuning range of the QVCOs reaches 33.09% and their phase noise is -119d8/Hz similar to 124d8/Hz @1MHz. Its current is less than 12mA at a 1.2V voltage supply when it operates at the highest frequency of 6.2GHz.

Frequency limitation in calibrating microwave test fixtures

The problem of frequency limitation arising in calibration of the test fixtures is investigated in this paper. It is found that at some frequencies periodically, the accuracy of the methods becomes very low, and. the denominators of the expressions of the required S-parameters approach zero. This conclusion can be drawn whether-the test fixtures, are symmetric or not. A good agreement between theory and experiment is obtained.

The Compact Pulsed Hadron Source: A Design Perspective

During the past. decades, large-scale national neutron sources have been developed in Asia, Europe, and North America. Complementing such efforts, compact hadron beam complexes and neutron sources intended to serve primarily universities and industrial institutes have been proposed, and some have recently been established. Responding to the demand in China for pulsed neutron/proton-beam platforms that are dedicated to fundamental and applied research for users in multiple disciplines from materials characterization to hadron therapy and radiography to accelerator-driven sub-critical reactor systems (ADS) for nuclear waste transmutation, we have initiated the construction of a compact, yet expandable, accelerator complex-the Compact Pulsed Hadron Source (CPHS). It consists of an accelerator front-end (a high-intensity ion source, a 3-MeV radio-frequency quadrupole linac (RFQ), and a 13-MeV drift-tube linac (DTL)), a neutron target station (a beryllium target with solid methane and room-temperature water moderators/reflector), and experimental stations for neutron imaging/radiography, small-angle scattering, and proton irradiation. In the future, the CPHS may also serve as an injector to a ring for proton therapy and radiography or as the front end to an ADS test facility. In this paper, we describe the design of the CPHS technical systems and its intended operation.