Deceptive female oviposition behaviour elicits male ejaculation in the European bitterling

In European bitterling Rhodeus amarus, fish that lay their eggs in the gill chambers of living freshwater mussels, females perform conspicuous behaviours associated with spawning that increases the probability of males performing ejaculatory behaviour and participating in a spawning. A significant positive association was detected between behaviour in which a female performs a spawning action but without releasing eggs, here termed 'deceptive female oviposition', and ejaculatory behaviour by courting males.

A possible evolutionary lag in the relationship between freshwater mussels and European bitterling

The coevolutionary dynamics between European bitterling Rhodeus amarus and freshwater unionid mussels, which the former parasitize by laying eggs on their gills, were tested. In a series of experiments fish preferences and mussel responses were compared in parasites and hosts of recent (Europe) and ancient (Asia) sympatry. Rhodeus amarus readily oviposited on the gills of all mussel species tested. Fish that laid their eggs on the gills of Asian Anodonta woodiana, however, suffered a dramatic reduction in reproductive success compared to fish that oviposited on the gills of European mussels: Unio pictorum, Unio tumidus, Anodonta anatina and Anodonta cygnea. This difference was the result of egg ejection behaviour by mussels rather than the unsuitability of the internal gill environment for European bitterling embryo development. The ejection response of mussels with a long sympatry with European bitterling was considerably more pronounced than that of mussels with a substantially shorter sympatry. The data support a coevolutionary arms race between bitterling and mussels and point to an evolutionary lag in the relationship between R. amarus and its European mussel hosts. (c) 2007 The Authors. Journal compilation (c) 2007 The Fisheries Society of the British Isles.

Effect of plant architecture on the structure of epiphytic macro invertebrate communities in a Chinese lake

We examined the effect of different plant architecture types on epiphytic macroinvertebrates of a shallow macrophyte-dominated lake in China. Macroinvertebrates were sampled from four dominant submersed macrophytes in the lake - two dissected plants (Myriophyllum spicatum L. and Ceratophyllum demersum L.) and two undissected plants (Potamogeton maackianus A. Benn. and Vallisneria spiralis L.). Macro invertebrate richness showed significant differences among four submersed macrophyte habitats, and higher density per g of dry plant were associated with dissected plants than undissected plants. The average abundance in dissected plants was as three-six times as in undissected plants. The biodiversity of epiphytic macroinvertebrates was higher in dissected plants than undissected plants. Our results suggest that dissected plants provide different habitat for macroinvertebrates than dissected plant, and this concurs with the hypothesis that the former could support more epiphytic macroinvertebrates than the latter.

Effect of cycles of feed deprivation on growth and food consumption of immature three-spined sticklebacks and European minnows

Individual juvenile three-spined sticklebacks Gasterosteus aculeatus and European minnow Phoxinus phoxinus, from sympatric populations, were subjected to four cycles of I week of food deprivation and 2 weeks of ad libitum feeding. Mean specific growth rate during the weeks of deprivation was negative and did not differ between species. The three-spined stickleback showed sufficient growth compensation to recover to the growth trajectory shown by control fish daily fed ad libitum. The compensation was generated by hyperphagia during the re-feeding periods, and in the last two periods of re-feeding, the gross growth efficiencies of deprived three-spined sticklebacks were greater than in control fish. The expression of the compensatory changes in growth and food consumption became clearer over the successive periods of re-feeding. The European minnow developed only a weak compensatory growth response and the mass trajectory of the deprived fish deviated more and more from the control trajectory During re-feeding periods, there were no significant differences in food consumption or gross growth efficiency between control and deprived European minnows. The differences between the two species are discussed in terms of the possible costs of compensatory growth, the control of growth and differences in feeding biology (C) 2003 The Fisheries Society of the British Isles.

Genetic divergence between Cyprinus carpio carpio and Cyprinus carpio haematopterus as assessed by mitochondrial DNA analysis, with emphasis on origin of European domestic carp

Although common carp is the major fish species in Asian and European aquaculture and many domestic varieties have occurred, there is a controversy about the origination of European domestic common carp. Some scientists affirmed that the ancestor of European domestic common carp was Danube River wild common carp, but others considered it might be Asian common carp. For elucidating origination of European domestic common carp, we chose two representative European domestic common carp strains (German mirror carp and Russian scattered scaled mirror carp) and one wild common carp strain of Cyprinus carpio carpio subspecies (Volga River wild common carp) and two Asian common carp strains, the Yangtze River wild common carp (Cyprinus carpio haematopterus) and traditionally domestic Xingguo red common carp, as experimental materials. ND5-ND6 and D-loop segments of mitochondrial DNA were amplified by polymerase chain reaction and analyzed through restriction fragment length polymorphism (RFLP) and sequencing respectively. The results revealed that HaeIII and DdeI digestion patterns of ND5-ND6 segment and sequences of control region were different between European subspecies C. carpio carpio and Asian subspecies C. carpio haematopterus. Phylogenetic analysis showed that German mirror carp and Russian scattered scaled mirror carp belonged to two subspecies, C. carpio carpio and C. carpio haematopterus, respectively. Therefore, there were different ancestors for domestic carp in Europe: German mirror carp was domesticated from European subspecies C. carpio carpio and Russian scattered scaled mirror carp originated from Asian subspecies C. carpio haematopterus.

A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Complex BPF with On Chip Auto-tuning Architecture for Low-IF Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 mu m standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 19dBm, with 50 Omega as the source impedance. The input referred noise is about 80 mu V-rms. The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28x0.22mm(2), less than 1/8 of that of the main-filter which is 0.92x0.59mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

An adaptive frequency synthesizer architecture reducing reference sidebands

An adaptive phase-locked loop (PLL) frequency synthesizer architecture for reducing reference sidebands at the output of the frequency synthesizer is described. The architecture combines two tuning loops: one is the main loop for locking the PLL frequency synthesizer and operating all the time, the other one is auxiliary loop for reducing reference sidebands and operating only when the main loop is closely locked. A 1.8V 1GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a 0.18um CMOS process. The suppression of the reference sidebands of the proposed frequency synthesizer is 13.8dB more than that of the general frequency synthesizer.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

Performance of an embedded optical vector matrix multiplication processor architecture

An embedded architecture of optical vector matrix multiplier (OVMM) is presented. The embedded architecture is aimed at optimising the data flow of vector matrix multiplier (VMM) to promote its performance. Data dependence is discussed when the OVMM is connected to a cluster system. A simulator is built to analyse the performance according to the architecture. According to the simulation, Amdahl's law is used to analyse the hybrid opto-electronic system. It is found that the electronic part and its interaction with optical part form the bottleneck of system.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Layered Architecture for Secure E-Commerce Applications

We present a layered architecture for secure e-commerce applications and protocols with fully automated dispute-resolution process, robust to communication failures and malicious faults. Our design is modular, with precise yet general-purpose interfaces and functionalities, and allows usage as an underlying secure service to different e-commerce, e-banking and other distributed systems. The interfaces support diverse, flexible and extensible payment scenarios and instruments, including direct buyer-seller payments as well as (the more common) indirect payments via payment service providers (e.g. banks). Our design is practical, efficient, and ensures reliability and security under realistic failure and delay conditions.