A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

A High Speed, 12-Channel Parallel, Monolithic Integrated CMOS OEIC Receiver

The design and fabrication of a high speed, 12-channel monolithic integrated CMOS optoelectronic integrated circuit(OEIC) receiver are reported.Each channel of the receiver consists of a photodetector,a transimpedance amplifier,and a post-amplifier.The double photodiode structure speeds up the receiver but hinders responsivity.The adoption of active inductors in the TIA circuit extends the-3dB bandwidth to a higher level.The receiver has been realized in a CSMC 0.6μm standard CMOS process.The measured results show that a single channel of the receiver is able to work at bit rates of 0.8～1.4Gb/s. Altogether, the 12-channel OEIC receiver chip can be operated at 15Gb/s.

Bandwidth Design for CMOS Monolithic Photoreceiver

A monolithic photoreceiver which consists of a double photodiode (DPD) detector and a regulated cascade(RGC) transimpedance amplifier (TIA) is designed. The small signal circuit model of DPD is given and the band width design method of a monolithic photoreceiver is presented. An important factor which limits the bandwidth of DPD detector and the photoreceiver is presented and analyzed in detail. A monolithic photoreceiver with 1.71GHz bandwidth and 49dB transimpedance gain is designed and simulated by applying a low-cost 0. 6um CMOS process and the test result is given.

Design and fabrication of polarization-insensitive 1550 mm semiconductor optical amplifiers

Polarization-insensitive semiconductor optical amplifiers (SOA's) with tensile-strained multi-quantum-wells as actice regions are designed and fabricated. The 6x6 Luttinger-Kohn model and Bir-Pikus Hamiltonian are employed to calculate the valence subband structures of strained quantum wells, and then a Lorentzian line-shape function is combined to calculate the material gain spectra for TE and TM modes. The device structure for polarization insensitive SOA is designed based on the materialde gain spectra of TE and TM modes and the gain factors for multilayer slab waveguide. Based on the designed structure parameters, we grow the SOA wafer by MOCVD and get nearly magnitude of output power for TE and TM modes from the broad-area semiconductor lasers fabricated from the wafer.

高计数率下的四路反堆积放大电路

A quadruple rejected-pile up amplifier used for high counting rate up to 105/s of average counting rate was described in this paper.To meet the need of high counting rate,the baseline regulation fuction,rejected pile up fuction was designed in the amplifier and the mark of rejected pile up was given for treatment of successive circuits.The quadruple amplifier consisting of four same circuits was assembled in one single NIM modul.These circuits have the advantages of compact construction,small volume and sta...中文文摘：介绍一种在高计数率情况下的反堆积放大器,它允许通过的平均计数为105/s。该放大器为了适应高计数率的要求,设计了基线调节功能和反堆积功能,给出了堆积标志,以便后继电路的处理。该电路在一个单宽NIM插件中有完全相同的四路电路工作,结构紧凑,体积小,工作性能稳定。

基于CMOS器件的专用放大电路设计

随着国家大科学工程兰州重离子加速器冷却储存环(HIRFL-CSR)建成，CSRm实验探测系统也正在建设当中。CSRm实验探测系统具有多种探测器数万个探测单元。对于这样先进的探测器和大型实验探测系统采用传统的电子学仪器和方法已经无法构成读出电子学系统和数据获取系统，对前端读出电子学系统、数据获取系统提出更高的要求。因此，采用专用集成电路芯片(ASIC)构成前端读出电子学系统是最可行的方法。本论文所述的基于MOS管的专用放大电路设计正是基于集成电路（ASIC）芯片构建前端读出电子学系统的前期研究子部分。作为ASIC前端读出电子学研究的一部分，本论文主要阐述基于MOS器件的放大电路的研究，主要包括以下内容： 1、设计及实现基于CMOS管的电荷灵敏前置放大器，最后给出制作PCB板后的实验室调试结果； 2、设计仿真基于DMOS管的电荷灵敏前置放大器，对仿真结果进行讨论； 3、利用集成电路设计软件Tanner Pro实现电荷灵敏前置放大器的物理版图设计

强流扇聚焦回旋加速器中空间电荷效应的研究

本文比较系统地介绍了扇聚焦回旋加速器内部的束流动力学及其注入系统的一般理论，并结合两台具体的扇聚焦回旋加速器的设计讨论了在回旋加速器以及静电反射镜内空间电荷效应对束流的影响。第一章简单介绍了回旋加速器的发展历史及分类、强流回旋加速器的应用，加速器驱动系统ADS(Accelerator Driving System)、能量放大器EA(Energy Amplifier)方案以及本文工作的主要内容。第二章首先介绍了扇聚焦回旋加速器的基本理论，包括扇聚焦回旋加速器内的轨道理论(静态平衡轨道及加速轨道性质)以及相空间的描述方法等。然后详细讨论了回旋加速器内空间电荷效应的影响及研究方法，包括空间电荷作用下粒子的运动方程、空间电荷电场的不同种类、求解空间电荷电场的基本方法和模型以及空间电荷效应对束流轨道特性和相空间传输特性的影响等。在本章的第4节中，介绍了两台强流扇聚焦回旋加速器(50MeV-6mA H_2~+超导扇聚焦回旋加速器和17MeV-2mA H~-扇聚焦回旋加速器)的具体设计步骤和计算结果,讨论了这两台扇聚焦回旋加速器中加速轨道和相空间的传输以及空间电荷效应的影响。最后，简单介绍了设计时所使用的两个计算程序AGORA_SCE和CINEZ_SCE。第三章首先简单介绍了用于扇聚焦回旋加速器的各种注入方法以及在轴向注入时所采用的不同种类的静电偏转镜。然后详细介绍了目前最常用的螺旋扇型静电偏转镜的基本工作原理，如参考粒子的运动轨道及偏转镜的光学性质等，讨论了螺旋线型静电偏转镜中空间电荷效应的影响。最后仍然以50MeV-6mAH_2~+和17MeV-2mA H~-这两台扇聚焦回旋加速器为例，对它们的静电偏转镜进行了设计，并分别研究了它们在空间电荷效应影响下的轨道特性及相空间传输特性。第四章简单介绍了工作中所用到的一些计算工具，如三维电磁场计算程序MAFIA以及等时场分析程序EQUIL，并给出了17MeV-2mA H~-扇聚焦回旋加速器的等时场的计算结果。论文的最后部分简单总结了本文的工作，并提出了今后进一步的工作设想。

Fabrication and spectroscopic broadening properties for 1.5 mu m amplification of Er3+-doped BaF2 nanoparticles

We show the potential application of Er3+-doped BaF2 nanoparticles prepared from microemulsion technology for 1.5 mu m amplification in telecommunication. Nanoparticles with different sizes of about 8, 10, and 20.5 nm were prepared. The XRD patterns showed the excursion of diffraction peaks. When the particle size is smaller or the diffraction angle is larger, this kind of excursion will be more serious.

一种低功耗微弱信号放大电路的优化设计与研究

针对远距离声源发射的水声信号微弱、水声接收设备电源能量有限的特点,提出一种功耗小、对无源元件误差灵敏度低、高增益放大的微弱水声信号通用放大电路。系统采用场效应管共源单调谐放大器为前置放大级,由四级级联低功耗运放构成带通滤波放大电路,省去传统的R、C低通网络,实现了对微弱水声信号的高增益放大和海洋背景噪声的归一化处理。通过计算电路网络传递函数极点证明了电路系统的稳定性。海上使用表明系统具有精度高、适应性强、电路稳定性好、功耗小等优点。