A direct-conversion mixer with a DC-offset cancellation for WLAN

This paper presents a 5GHz double-balanced mixer with DC-offset cancellation circuit for direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard. The analog feedback loop is used, to eliminate the DC-offset at the output of the double-balanced mixer. The test results show that the mixer with DC-offset cancellation circuit has voltage conversion gain of 9.5dB at 5.15GHz, noise figure of 13.5dB, IIP3 of 7.6 dBm, 1.73mV DC-offset voltage and 67mW power with 3.3-V power supply. The DC-offset cancellation circuit has less than 0.1mm(2) additional area and 0.3mW added power dissipation. The direct conversion WLAN receiver has been implemented in a 0.35 mu m SiGe BiCMOS technology.

A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver

A DC-offset cancellation scheme in the 5GHz direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard is described in this paper. It uses the analog feedback loop to eliminate the DC-offset at the output of the double-balanced mixer. The mixer has a simulation voltage conversion gain of IMB at 5.2GHz, noise figure of 9.67dB, IIP3 of 7.6dBm. The solution provides 39.1dB reduction according to the leakage value at LO and mixer load resistors, the additional noise figure added to mixer is less than 0.9dB, the added power dissipation is 0.1mW and was fabricated in 60GHz 0.35 mu m SiGe BiCMOS technology.

无线局域网的Web缓存系统研究

由于无线环境中的网络和手持设备的限制,缓存机制在提高移动系统性能方面发挥着重要作用。本文描述了适用于无线LAN的Web缓存系统EasyCache系统的实现,给出了基于数据挖掘理论的移动主机端缓存数据预取算法SEDP。模拟实验数据表明SEDP算法取得了良好的效果。

仿人机器人控制系统的研究与实现

根据仿人机器人控制性能的要求,设计开发了关节控制器,并通过CAN总线把各个关节控制器、力传感器及上位机连接在一起,构成了分布式控制系统.利用无线局域网技术,实现了语音、视频等多媒体信息的传输,把监控台、头部、上身和移动平台连接在一起,构成了仿人机器人完整的控制系统.最后提出了一些设想以提高系统的性能.

仿人机器人系统的研究与实现

针对仿人机器人的结构和控制性能的要求,设计开发了机器人的关节控制器,并利用CAN总线把各个关节和力传感器及上位机连接在一起,构成了有效可靠的分布式控制系统;利用无线局域网技术,实现了语音、视频等多媒体信息的传输,构成了仿人机器人完整的控制系统。最后提出了一些设想以提高系统的性能。

Wireless optical communication-based spatial pattern

We propose a novel communication technique which utilizes a set of mutually distinguishable optical patterns instead of convergent facula to transmit information. The communication capacity is increased by exploiting the optical spatial bandwidth resources. An optimum detector for this communication is proposed based on maximum-likelihood decision. The fundamental rule of designing signal spatial pattern is formulated from analysis of the probability of error decision. Finally, we present a typical electro-optical system scheme of the proposed communication. (c) 2006 Elsevier GmbH. All rights reserved.

Far-field spot compression without energy loss in main lob in wireless laser communication

Far-field spot compression without energy loss in main lob is of great significance to wireless laser communication. In this letter, we propose two schemes to obtain far-field spot compression without energy loss in main lob. One scheme is based on the simulated annealing (SA) algorithm. Using SA algorithm, we design the phase profile of the diffractive phase element (DPE). Using the designed DPE, far-field spot compression without energy loss in main lob is achieved. The other scheme is based on YG algorithm. By means of YG algorithm, we appropriately designed the DPE in the emitting plane. Using the DPE, far-field spot compression without energy loss in main lob is obtained. (c) 2007 Elsevier GmbH. All rights reserved.

A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

Low Power Integrated Circuits for Wireless Neural Recording Applications

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit, a clock recovery circuit and a power detector. The amplifiers were designed with a limited bandwidth for neural signals acquisition. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments. 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 MHz carrier within 10 mm. The total gain of 60 dB was obtained by the preamplifier and a main amplifier at 0.95Hz - 13.41 KHz with 0.215 mW power dissipation. The power consumption of the 100 MHz ASK transmitter is 0.374 mW. All the integrated circuits operated under a 3.3 V power supply except the voltage regulator.

Implantable Microsystem for Wireless Neural Recording Applications

A prototype microsystem is presented for wireless neural recording application. An inductive link was built for transcutaneous wireless power transfer and data transmission. Total 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 - 5 MHz with a distance of 0-10 mm. The integrated amplifiers were designed with a limited bandwidth for neural signals acquisition. The gain of 60 dB was obtained by preamplifier at 7 Hz - 3 KHz. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments with 0.374 - 2 mW power comsumption and a maximum data rate of 500 Kbps at 100 MHz. All the integrated circuits modules except the power recovery circuit were tested or stimulated under a 3.3 V power supply, and fabricated in standard CMOS processing.