Electrical and optical interconnects for high-performance computing

Technology scaling has enabled drastic growth in the computational and storage capacity of integrated circuits (ICs). This constant growth drives an increasing demand for high-bandwidth communication between and within ICs. In this dissertation we focus on low-power solutions that address this demand. We divide communication links into three subcategories depending on the communication distance. Each category has a different set of challenges and requirements and is affected by CMOS technology scaling in a different manner. We start with short-range chip-to-chip links for board-level communication. Next we will discuss board-to-board links, which demand a longer communication range. Finally on-chip links with communication ranges of a few millimeters are discussed.

Electrical signaling is a natural choice for chip-to-chip communication due to efficient integration and low cost. IO data rates have increased to the point where electrical signaling is now limited by the channel bandwidth. In order to achieve multi-Gb/s data rates, complex designs that equalize the channel are necessary. In addition, a high level of parallelism is central to sustaining bandwidth growth. Decision feedback equalization (DFE) is one of the most commonly employed techniques to overcome the limited bandwidth problem of the electrical channels. A linear and low-power summer is the central block of a DFE. Conventional approaches employ current-mode techniques to implement the summer, which require high power consumption. In order to achieve low-power operation we propose performing the summation in the charge domain. This approach enables a low-power and compact realization of the DFE as well as crosstalk cancellation. A prototype receiver was fabricated in 45nm SOI CMOS to validate the functionality of the proposed technique and was tested over channels with different levels of loss and coupling. Measurement results show that the receiver can equalize channels with maximum 21dB loss while consuming about 7.5mW from a 1.2V supply. We also introduce a compact, low-power transmitter employing passive equalization. The efficacy of the proposed technique is demonstrated through implementation of a prototype in 65nm CMOS. The design achieves up to 20Gb/s data rate while consuming less than 10mW.

An alternative to electrical signaling is to employ optical signaling for chip-to-chip interconnections, which offers low channel loss and cross-talk while providing high communication bandwidth. In this work we demonstrate the possibility of building compact and low-power optical receivers. A novel RC front-end is proposed that combines dynamic offset modulation and double-sampling techniques to eliminate the need for a short time constant at the input of the receiver. Unlike conventional designs, this receiver does not require a high-gain stage that runs at the data rate, making it suitable for low-power implementations. In addition, it allows time-division multiplexing to support very high data rates. A prototype was implemented in 65nm CMOS and achieved up to 24Gb/s with less than 0.4pJ/b power efficiency per channel. As the proposed design mainly employs digital blocks, it benefits greatly from technology scaling in terms of power and area saving.

As the technology scales, the number of transistors on the chip grows. This necessitates a corresponding increase in the bandwidth of the on-chip wires. In this dissertation, we take a close look at wire scaling and investigate its effect on wire performance metrics. We explore a novel on-chip communication link based on a double-sampling architecture and dynamic offset modulation technique that enables low power consumption and high data rates while achieving high bandwidth density in 28nm CMOS technology. The functionality of the link is demonstrated using different length minimum-pitch on-chip wires. Measurement results show that the link achieves up to 20Gb/s of data rate (12.5Gb/s/$\mu$m) with better than 136fJ/b of power efficiency.

Cloud computing services for seismic networks

This thesis describes a compositional framework for developing situation awareness applications: applications that provide ongoing information about a user's changing environment. The thesis describes how the framework is used to develop a situation awareness application for earthquakes. The applications are implemented as Cloud computing services connected to sensors and actuators. The architecture and design of the Cloud services are described and measurements of performance metrics are provided. The thesis includes results of experiments on earthquake monitoring conducted over a year. The applications developed by the framework are (1) the CSN --- the Community Seismic Network --- which uses relatively low-cost sensors deployed by members of the community, and (2) SAF --- the Situation Awareness Framework --- which integrates data from multiple sources, including the CSN, CISN --- the California Integrated Seismic Network, a network consisting of high-quality seismometers deployed carefully by professionals in the CISN organization and spread across Southern California --- and prototypes of multi-sensor platforms that include carbon monoxide, methane, dust and radiation sensors.

Nanostructured tungsten trioxide photoanodes for solar energy conversion

Nanostructured tungsten trioxide (WO₃) photoelectrodes are potential candidates for the anodic portion of an integrated solar water-splitting device that generates hydrogen fuel and oxygen from water. These nanostructured materials can potentially offer improved performance in photooxidation reactions compared to unstructured materials because of enhancements in light scattering, increases in surface area, and their decoupling of the directions of light absorption and carrier collection. To evaluate the presence of these effects and their contributions toward energy conversion efficiency, a variety of nanostructured WO₃ photoanodes were synthesized by electrodeposition within nanoporous templates and by anodization of tungsten foils. A robust fabrication process was developed for the creation of oriented WO₃ nanorod arrays, which allows for control nanorod diameter and length. Films of nanostructured WO₃ platelets were grown via anodization, the morphology of the films was controlled by the anodization conditions, and the current-voltage performance and spectral response properties of these films were studied. The observed photocurrents were consistent with the apparent morphologies of the nanostructured arrays. Measurements of electrochemically active surface area and other physical characteristics were correlated with observed differences in absorbance, external quantum yield, and photocurrent density for the anodized arrays. The capability to quantify these characteristics and relate them to photoanode performance metrics can allow for selection of appropriate structural parameters when designing photoanodes for solar energy conversion.

Chemical and Electrochemical Behavior of Graphene-Covered Silicon Photoanodes

This dissertation describes efforts over the last five years to develop protective layers for semiconductor photoelectrodes based on monolayer or few-layer graphene sheets. Graphene is an attractive candidate for a protective layer because of its known chemical inertness, transparency, ease of deposition, and limited number of electronic states. Monolayer graphene was found to effectively inhibit loss of photocurrent over 1000 seconds at n-Si/aqueous electrolyte interfaces that exhibit total loss over photocurrent over 100 seconds. Further, the presence of graphene was found to effect only partial Fermi level pinning at the Si/graphene interface with respect to a range of nonaqueous electrolytes. Fluorination of graphene was found to extend the stability imparted on n-Si by the monolayer sheet in aqueous Fe(CN)₆^3-/4- electrolyte to over 100,000 seconds. It was demonstrated that the stability of the photocurrent of n-Si/fluorinated graphene/aqueous electrolyte interfaces relative to n-Si/aqueous electrolyte interfaces is likely attributable to the inhibition of oxidation of the silicon surface.

This dissertation also relates efforts to describe and define terminology relevant to the field of photoelectrochemistry and solar fuels production. Terminology describing varying interfaces employed in electrochemical solar fuels devices are defined, and the research challenges associated with each are discussed. Methods for determining the efficiency of varying photoelectrochemical and solar-fuel-producing cells from the current-voltage behavior of the individual components of such a device without requiring the device be constructed are described, and a range of commonly employed performance metrics are explored.