Electrical and optical interconnects for high-performance computing

Technology scaling has enabled drastic growth in the computational and storage capacity of integrated circuits (ICs). This constant growth drives an increasing demand for high-bandwidth communication between and within ICs. In this dissertation we focus on low-power solutions that address this demand. We divide communication links into three subcategories depending on the communication distance. Each category has a different set of challenges and requirements and is affected by CMOS technology scaling in a different manner. We start with short-range chip-to-chip links for board-level communication. Next we will discuss board-to-board links, which demand a longer communication range. Finally on-chip links with communication ranges of a few millimeters are discussed.

Electrical signaling is a natural choice for chip-to-chip communication due to efficient integration and low cost. IO data rates have increased to the point where electrical signaling is now limited by the channel bandwidth. In order to achieve multi-Gb/s data rates, complex designs that equalize the channel are necessary. In addition, a high level of parallelism is central to sustaining bandwidth growth. Decision feedback equalization (DFE) is one of the most commonly employed techniques to overcome the limited bandwidth problem of the electrical channels. A linear and low-power summer is the central block of a DFE. Conventional approaches employ current-mode techniques to implement the summer, which require high power consumption. In order to achieve low-power operation we propose performing the summation in the charge domain. This approach enables a low-power and compact realization of the DFE as well as crosstalk cancellation. A prototype receiver was fabricated in 45nm SOI CMOS to validate the functionality of the proposed technique and was tested over channels with different levels of loss and coupling. Measurement results show that the receiver can equalize channels with maximum 21dB loss while consuming about 7.5mW from a 1.2V supply. We also introduce a compact, low-power transmitter employing passive equalization. The efficacy of the proposed technique is demonstrated through implementation of a prototype in 65nm CMOS. The design achieves up to 20Gb/s data rate while consuming less than 10mW.

An alternative to electrical signaling is to employ optical signaling for chip-to-chip interconnections, which offers low channel loss and cross-talk while providing high communication bandwidth. In this work we demonstrate the possibility of building compact and low-power optical receivers. A novel RC front-end is proposed that combines dynamic offset modulation and double-sampling techniques to eliminate the need for a short time constant at the input of the receiver. Unlike conventional designs, this receiver does not require a high-gain stage that runs at the data rate, making it suitable for low-power implementations. In addition, it allows time-division multiplexing to support very high data rates. A prototype was implemented in 65nm CMOS and achieved up to 24Gb/s with less than 0.4pJ/b power efficiency per channel. As the proposed design mainly employs digital blocks, it benefits greatly from technology scaling in terms of power and area saving.

As the technology scales, the number of transistors on the chip grows. This necessitates a corresponding increase in the bandwidth of the on-chip wires. In this dissertation, we take a close look at wire scaling and investigate its effect on wire performance metrics. We explore a novel on-chip communication link based on a double-sampling architecture and dynamic offset modulation technique that enables low power consumption and high data rates while achieving high bandwidth density in 28nm CMOS technology. The functionality of the link is demonstrated using different length minimum-pitch on-chip wires. Measurement results show that the link achieves up to 20Gb/s of data rate (12.5Gb/s/$\mu$m) with better than 136fJ/b of power efficiency.

Wire array photovoltaics

Over the past five years, the cost of solar panels has dropped drastically and, in concert, the number of installed modules has risen exponentially. However, solar electricity is still more than twice as expensive as electricity from a natural gas plant. Fortunately, wire array solar cells have emerged as a promising technology for further lowering the cost of solar.

Si wire array solar cells are formed with a unique, low cost growth method and use 100 times less material than conventional Si cells. The wires can be embedded in a transparent, flexible polymer to create a free-standing array that can be rolled up for easy installation in a variety of form factors. Furthermore, by incorporating multijunctions into the wire morphology, higher efficiencies can be achieved while taking advantage of the unique defect relaxation pathways afforded by the 3D wire geometry.

The work in this thesis shepherded Si wires from undoped arrays to flexible, functional large area devices and laid the groundwork for multijunction wire array cells. Fabrication techniques were developed to turn intrinsic Si wires into full p-n junctions and the wires were passivated with a-Si:H and a-SiNx:H. Single wire devices yielded open circuit voltages of 600 mV and efficiencies of 9%. The arrays were then embedded in a polymer and contacted with a transparent, flexible, Ni nanoparticle and Ag nanowire top contact. The contact connected >99% of the wires in parallel and yielded flexible, substrate free solar cells featuring hundreds of thousands of wires.

Building on the success of the Si wire arrays, GaP was epitaxially grown on the material to create heterostructures for photoelectrochemistry. These cells were limited by low absorption in the GaP due to its indirect bandgap, and poor current collection due to a diffusion length of only 80 nm. However, GaAsP on SiGe offers a superior combination of materials, and wire architectures based on these semiconductors were investigated for multijunction arrays. These devices offer potential efficiencies of 34%, as demonstrated through an analytical model and optoelectronic simulations. SiGe and Ge wires were fabricated via chemical-vapor deposition and reactive ion etching. GaAs was then grown on these substrates at the National Renewable Energy Lab and yielded ns lifetime components, as required for achieving high efficiency devices.

Identification of thermally-tagged coherent structures in the zero pressure gradient turbulent boundary layer

A zero pressure gradient boundary layer over a flat plate is subjected to step changes in thermal condition at the wall, causing the formation of internal, heated layers. The resulting temperature fluctuations and their corresponding density variations are associated with turbulent coherent structures. Aero-optical distortion occurs when light passes through the boundary layer, encountering the changing index of refraction resulting from the density variations. Instantaneous measurements of streamwise velocity, temperature and the optical deflection angle experienced by a laser traversing the boundary layer are made using hot and cold wires and a Malley probe, respectively. Correlations of the deflection angle with the temperature and velocity records suggest that the dominant contribution to the deflection angle comes from thermally-tagged structures in the outer boundary layer with a convective velocity of approximately 0.8U∞. An examination of instantaneous temperature and velocity and their temporal gradients conditionally averaged around significant optical deflections shows behavior consistent with the passage of a heated vortex. Strong deflections are associated with strong negative temperature gradients, and strong positive velocity gradients where the sign of the streamwise velocity fluctuation changes. The power density spectrum of the optical deflections reveals associated structure size to be on the order of the boundary layer thickness. A comparison to the temperature and velocity spectra suggests that the responsible structures are smaller vortices in the outer boundary layer as opposed to larger scale motions. Notable differences between the power density spectra of the optical deflections and the temperature remain unresolved due to the low frequency response of the cold wire.

Microelectrode Implants for Spinal Cord Stimulation in Rats

Paralysis is a debilitating condition afflicting millions of people across the globe, and is particularly deleterious to quality of life when motor function of the legs is severely impaired or completely absent. Fortunately, spinal cord stimulation has shown great potential for improving motor function after spinal cord injury and other pathological conditions. Many animal studies have shown stimulation of the neural networks in the spinal cord can improve motor ability so dramatically that the animals can even stand and step after a complete spinal cord transaction.

This thesis presents work to successfully provide a chronically implantable device for rats that greatly enhances the ability to control the site of spinal cord stimulation. This is achieved through the use of a parylene-C based microelectrode array, which enables a density of stimulation sites unattainable with conventional wire electrodes. While many microelectrode devices have been proposed in the past, the spinal cord is a particularly challenging environment due to the bending and movement it undergoes in a live animal. The developed microelectrode array is the first to have been implanted in vivo while retaining functionality for over a month. In doing so, different neural pathways can be selectively activated to facilitate standing and stepping in spinalized rats using various electrode combinations, and important differences in responses are observed.

An engineering challenge for the usability of any high density electrode array is connecting the numerous electrodes to a stimulation source. This thesis develops several technologies to address this challenge, beginning with a fully passive implant that uses one wire per electrode to connect to an external stimulation source. The number of wires passing through the body and the skin proved to be a hazard for the health of the animal, so a multiplexed implant was devised in which active electronics reduce the number of wires. Finally, a fully wireless implant was developed. As these implants are tested in vivo, encapsulation is of critical importance to retain functionality in a chronic experiment, especially for the active implants, and it was achieved without the use of costly ceramic or metallic hermetic packaging. Active implants were built that retained functionality 8 weeks after implantation, and achieved stepping in spinalized rats after just 8-10 days, which is far sooner than wire-based electrical stimulation has achieved in prior work.

Heteroepitaxy of Group IV and Group III-V semiconductor alloys for photovoltaic applications

Photovoltaic energy conversion represents a economically viable technology for realizing collection of the largest energy resource known to the Earth -- the sun. Energy conversion efficiency is the most leveraging factor in the price of energy derived from this process. This thesis focuses on two routes for high efficiency, low cost devices: first, to use Group IV semiconductor alloy wire array bottom cells and epitaxially grown Group III-V compound semiconductor alloy top cells in a tandem configuration, and second, GaP growth on planar Si for heterojunction and tandem cell applications.

Metal catalyzed vapor-liquid-solid grown microwire arrays are an intriguing alternative for wafer-free Si and SiGe materials which can be removed as flexible membranes. Selected area Cu-catalyzed vapor-liquid solid growth of SiGe microwires is achieved using chlorosilane and chlorogermane precursors. The composition can be tuned up to 12% Ge with a simultaneous decrease in the growth rate from 7 to 1 μm/min^-1. Significant changes to the morphology were observed, including tapering and faceting on the sidewalls and along the lengths of the wires. Characterization of axial and radial cross sections with transmission electron microscopy revealed no evidence of defects at facet corners and edges, and the tapering is shown to be due to in-situ removal of catalyst material during growth. X-ray diffraction and transmission electron microscopy reveal a Ge-rich crystal at the tip of the wires, strongly suggesting that the Ge incorporation is limited by the crystallization rate.

Tandem Ga_1-xIn_xP/Si microwire array solar cells are a route towards a high efficiency, low cost, flexible, wafer-free solar technology. Realizing tandem Group III-V compound semiconductor/Si wire array devices requires optimization of materials growth and device performance. GaP and Ga_1-xIn_xP layers were grown heteroepitaxially with metalorganic chemical vapor deposition on Si microwire array substrates. The layer morphology and crystalline quality have been studied with scanning electron microscopy and transmission electron microscopy, and they provide a baseline for the growth and characterization of a full device stack. Ultimately, the complexity of the substrates and the prevalence of defects resulted in material without detectable photoluminescence, unsuitable for optoelectronic applications.

Coupled full-field optical and device physics simulations of a Ga_0.51In_0.49P/Si wire array tandem are used to predict device performance. A 500 nm thick, highly doped "buffer" layer between the bottom cell and tunnel junction is assumed to harbor a high density of lattice mismatch and heteroepitaxial defects. Under simulated AM1.5G illumination, the device structure explored in this work has a simulated efficiency of 23.84% with realistic top cell SRH lifetimes and surface recombination velocities. The relative insensitivity to surface recombination is likely due to optical generation further away from the free surfaces and interfaces of the device structure.

Finally, GaP has been grown free of antiphase domains on Si (112) oriented substrates using metalorganic chemical vapor deposition. Low temperature pulsed nucleation is followed by high temperature continuous growth, yielding smooth, specular thin films. Atomic force microscopy topography mapping showed very smooth surfaces (4-6 Å RMS roughness) with small depressions in the surface. Thin films (~ 50 nm) were pseudomorphic, as confirmed by high resolution x-ray diffraction reciprocal space mapping, and 200 nm thick films showed full relaxation. Transmission electron microscopy showed no evidence of antiphase domain formation, but there is a population of microtwin and stacking fault defects.

Paths Towards High Efficiency Silicon Photovoltaics

While photovoltaics hold much promise as a sustainable electricity source, continued cost reduction is necessary to continue the current growth in deployment. A promising path to continuing to reduce total system cost is by increasing device efficiency. This thesis explores several silicon-based photovoltaic technologies with the potential to reach high power conversion efficiencies. Silicon microwire arrays, formed by joining millions of micron diameter wires together, were developed as a low cost, low efficiency solar technology. The feasibility of transitioning this to a high efficiency technology was explored. In order to achieve high efficiency, high quality silicon material must be used. Lifetimes and diffusion lengths in these wires were measured and the action of various surface passivation treatments studied. While long lifetimes were not achieved, strong inversion at the silicon / hydrofluoric acid interface was measured, which is important for understanding a common measurement used in solar materials characterization.

Cryogenic deep reactive ion etching was then explored as a method for fabricating high quality wires and improved lifetimes were measured. As another way to reach high efficiency, growth of silicon-germanium alloy wires was explored as a substrate for a III-V on Si tandem device. Patterned arrays of wires with up to 12% germanium incorporation were grown. This alloy is more closely lattice matched to GaP than silicon and allows for improvements in III-V integration on silicon.

Heterojunctions of silicon are another promising path towards achieving high efficiency devices. The GaP/Si heterointerface and properties of GaP grown on silicon were studied. Additionally, a substrate removal process was developed which allows the formation of high quality free standing GaP films and has wide applications in the field of optics.

Finally, the effect of defects at the interface of the amorphous silicon heterojuction cell was studied. Excellent voltages, and thus efficiencies, are achievable with this system, but the voltage is very sensitive to growth conditions. We directly measured lateral transport lengths at the heterointerface on the order of tens to hundreds of microns, which allows carriers to travel towards any defects that are present and recombine. This measurement adds to the understanding of these types of high efficiency devices and may aid in future device design.

Atomic-level structure and deformation in metallic glasses

Metallic glasses (MGs) are a relatively new class of materials discovered in 1960 and lauded for its high strengths and superior elastic properties. Three major obstacles prevent their widespread use as engineering materials for nanotechnology and industry: 1) their lack of plasticity mechanisms for deformation beyond the elastic limit, 2) their disordered atomic structure, which prevents effective study of their structure-to-property relationships, and 3) their poor glass forming ability, which limits bulk metallic glasses to sizes on the order of centimeters. We focused on understanding the first two major challenges by observing the mechanical properties of nanoscale metallic glasses in order to gain insight into its atomic-level structure and deformation mechanisms. We found that anomalous stable plastic flow emerges in room-temperature MGs at the nanoscale in wires as little as ~100 nanometers wide regardless of fabrication route (ion-irradiated or not). To circumvent experimental challenges in characterizing the atomic-level structure, extensive molecular dynamics simulations were conducted using approximated (embedded atom method) potentials to probe the underlying processes that give rise to plasticity in nanowires. Simulated results showed that mechanisms of relaxation via the sample free surfaces contribute to tensile ductility in these nanowires. Continuing with characterizing nanoscale properties, we studied the fracture properties of nano-notched MGnanowires and the compressive response of MG nanolattices at cryogenic (~130 K) temperatures. We learned from these experiments that nanowires are sensitive to flaws when the (amorphous) microstructure does not contribute stress concentrations, and that nano-architected structures with MG nanoribbons are brittle at low temperatures except when elastic shell buckling mechanisms dominate at low ribbon thicknesses (~20 nm), which instead gives rise to fully recoverable nanostructures regardless of temperature. Finally, motivated by understanding structure-to-property relationships in MGs, we studied the disordered atomic structure using a combination of in-situ X-ray tomography and X-ray diffraction in a diamond anvil cell and molecular dynamics simulations. Synchrotron X-ray experiments showed the progression of the atomic-level structure (in momentum space) and macroscale volume under increasing hydrostatic pressures. Corresponding simulations provided information on the real space structure, and we found that the samples displayed fractal scaling (r^d ∝ V, d < 3) at short length scales (< ~8 Å), and exhibited a crossover to a homogeneous scaling (d = 3) at long length scales. We examined this underlying fractal structure of MGs with parallels to percolation clusters and discuss the implications of this structural analogy to MG properties and the glass transition phenomenon.