Electrical and optical interconnects for high-performance computing

Technology scaling has enabled drastic growth in the computational and storage capacity of integrated circuits (ICs). This constant growth drives an increasing demand for high-bandwidth communication between and within ICs. In this dissertation we focus on low-power solutions that address this demand. We divide communication links into three subcategories depending on the communication distance. Each category has a different set of challenges and requirements and is affected by CMOS technology scaling in a different manner. We start with short-range chip-to-chip links for board-level communication. Next we will discuss board-to-board links, which demand a longer communication range. Finally on-chip links with communication ranges of a few millimeters are discussed.

Electrical signaling is a natural choice for chip-to-chip communication due to efficient integration and low cost. IO data rates have increased to the point where electrical signaling is now limited by the channel bandwidth. In order to achieve multi-Gb/s data rates, complex designs that equalize the channel are necessary. In addition, a high level of parallelism is central to sustaining bandwidth growth. Decision feedback equalization (DFE) is one of the most commonly employed techniques to overcome the limited bandwidth problem of the electrical channels. A linear and low-power summer is the central block of a DFE. Conventional approaches employ current-mode techniques to implement the summer, which require high power consumption. In order to achieve low-power operation we propose performing the summation in the charge domain. This approach enables a low-power and compact realization of the DFE as well as crosstalk cancellation. A prototype receiver was fabricated in 45nm SOI CMOS to validate the functionality of the proposed technique and was tested over channels with different levels of loss and coupling. Measurement results show that the receiver can equalize channels with maximum 21dB loss while consuming about 7.5mW from a 1.2V supply. We also introduce a compact, low-power transmitter employing passive equalization. The efficacy of the proposed technique is demonstrated through implementation of a prototype in 65nm CMOS. The design achieves up to 20Gb/s data rate while consuming less than 10mW.

An alternative to electrical signaling is to employ optical signaling for chip-to-chip interconnections, which offers low channel loss and cross-talk while providing high communication bandwidth. In this work we demonstrate the possibility of building compact and low-power optical receivers. A novel RC front-end is proposed that combines dynamic offset modulation and double-sampling techniques to eliminate the need for a short time constant at the input of the receiver. Unlike conventional designs, this receiver does not require a high-gain stage that runs at the data rate, making it suitable for low-power implementations. In addition, it allows time-division multiplexing to support very high data rates. A prototype was implemented in 65nm CMOS and achieved up to 24Gb/s with less than 0.4pJ/b power efficiency per channel. As the proposed design mainly employs digital blocks, it benefits greatly from technology scaling in terms of power and area saving.

As the technology scales, the number of transistors on the chip grows. This necessitates a corresponding increase in the bandwidth of the on-chip wires. In this dissertation, we take a close look at wire scaling and investigate its effect on wire performance metrics. We explore a novel on-chip communication link based on a double-sampling architecture and dynamic offset modulation technique that enables low power consumption and high data rates while achieving high bandwidth density in 28nm CMOS technology. The functionality of the link is demonstrated using different length minimum-pitch on-chip wires. Measurement results show that the link achieves up to 20Gb/s of data rate (12.5Gb/s/$\mu$m) with better than 136fJ/b of power efficiency.

Dynamic Stall on Vertical Axis Wind Turbines

In this study the dynamics of flow over the blades of vertical axis wind turbines was investigated using a simplified periodic motion to uncover the fundamental flow physics and provide insight into the design of more efficient turbines. Time-resolved, two-dimensional velocity measurements were made with particle image velocimetry on a wing undergoing pitching and surging motion to mimic the flow on a turbine blade in a non-rotating frame. Dynamic stall prior to maximum angle of attack and a leading edge vortex development were identified in the phase-averaged flow field and captured by a simple model with five modes, including the first two harmonics of the pitch/surge frequency identified using the dynamic mode decomposition. Analysis of these modes identified vortical structures corresponding to both frequencies that led the separation and reattachment processes, while their phase relationship determined the evolution of the flow.

Detailed analysis of the leading edge vortex found multiple regimes of vortex development coupled to the time-varying flow field on the airfoil. The vortex was shown to grow on the airfoil for four convection times, before shedding and causing dynamic stall in agreement with 'optimal' vortex formation theory. Vortex shedding from the trailing edge was identified from instantaneous velocity fields prior to separation. This shedding was found to be in agreement with classical Strouhal frequency scaling and was removed by phase averaging, which indicates that it is not exactly coupled to the phase of the airfoil motion.

The flow field over an airfoil undergoing solely pitch motion was shown to develop similarly to the pitch/surge motion; however, flow separation took place earlier, corresponding to the earlier formation of the leading edge vortex. A similar reduced-order model to the pitch/surge case was developed, with similar vortical structures leading separation and reattachment; however, the relative phase lead of the separation mode, corresponding to earlier separation, necessitated that a third frequency to be incorporated into the reattachment mode to provide a relative lag in reattachment.

Finally, the results are returned to the rotating frame and the effects of each flow phenomena on the turbine are estimated, suggesting kinematic criteria for the design of improved turbines.

The unsteady forces on slender delta wing hydrofoils oscillating in heave

The investigations described herein are both experimental and theoretical. An experimental technique is described by which the models tested could be oscillated sinusoidally in heave. The apparatus used to gather the unsteady lift, drag and pitching moment data is also described.

The models tested were two flat delta wings with apex angles of 15° and 30° and they had sharp leading edges to insure flow separation. The models were fabricated from 0.25 inch aluminum plate and were approximately one foot in length.

Three distinct types of flow were investigated: 1) fully wetted, 2) ventilated and 3) planing. The experimental data are compared with existing theories for steady motions in the case of fully wetted delta wings. Ventilation measurements, made only for the 30° model at 20° angle of attack, of lift and drag are presented.

A correction of the theory proposed by M.P. Tulin for high speed planing of slender bodies is presented and it is extended to unsteady motions. This is compared to the experimental measurements made at 6° and 12° angle of attack for the two models previously described.

This is the first extensive measurement of unsteady drag for any shape wing, the first measurement of unsteady planing forces, the first quantitative documentation of unstable oscillations near a free surface, and the first measurements of the unsteady forces on ventilated delta wings. The results of these investigations, both theoretical and experimental, are discussed and further investigations suggested.