Deep tissue fluorescence imaging with time-reversed light

Advances in optical techniques have enabled many breakthroughs in biology and medicine. However, light scattering by biological tissues remains a great obstacle, restricting the use of optical methods to thin ex vivo sections or superficial layers in vivo. In this thesis, we present two related methods that overcome the optical depth limit—digital time reversal of ultrasound encoded light (digital TRUE) and time reversal of variance-encoded light (TROVE). These two techniques share the same principle of using acousto-optic beacons for time reversal optical focusing within highly scattering media, like biological tissues. Ultrasound, unlike light, is not significantly scattered in soft biological tissues, allowing for ultrasound focusing. In addition, a fraction of the scattered optical wavefront that passes through the ultrasound focus gets frequency-shifted via the acousto-optic effect, essentially creating a virtual source of frequency-shifted light within the tissue. The scattered ultrasound-tagged wavefront can be selectively measured outside the tissue and time-reversed to converge at the location of the ultrasound focus, enabling optical focusing within deep tissues. In digital TRUE, we time reverse ultrasound-tagged light with an optoelectronic time reversal device (the digital optical phase conjugate mirror, DOPC). The use of the DOPC enables high optical gain, allowing for high intensity optical focusing and focal fluorescence imaging in thick tissues at a lateral resolution of 36 µm by 52 µm. The resolution of the TRUE approach is fundamentally limited to that of the wavelength of ultrasound. The ultrasound focus (~ tens of microns wide) usually contains hundreds to thousands of optical modes, such that the scattered wavefront measured is a linear combination of the contributions of all these optical modes. In TROVE, we make use of our ability to digitally record, analyze and manipulate the scattered wavefront to demix the contributions of these spatial modes using variance encoding. In essence, we encode each spatial mode inside the scattering sample with a unique variance, allowing us to computationally derive the time reversal wavefront that corresponds to a single optical mode. In doing so, we uncouple the system resolution from the size of the ultrasound focus, demonstrating optical focusing and imaging between highly diffusing samples at an unprecedented, speckle-scale lateral resolution of ~ 5 µm. Our methods open up the possibility of fully exploiting the prowess and versatility of biomedical optics in deep tissues.

Electrical and optical interconnects for high-performance computing

Technology scaling has enabled drastic growth in the computational and storage capacity of integrated circuits (ICs). This constant growth drives an increasing demand for high-bandwidth communication between and within ICs. In this dissertation we focus on low-power solutions that address this demand. We divide communication links into three subcategories depending on the communication distance. Each category has a different set of challenges and requirements and is affected by CMOS technology scaling in a different manner. We start with short-range chip-to-chip links for board-level communication. Next we will discuss board-to-board links, which demand a longer communication range. Finally on-chip links with communication ranges of a few millimeters are discussed.

Electrical signaling is a natural choice for chip-to-chip communication due to efficient integration and low cost. IO data rates have increased to the point where electrical signaling is now limited by the channel bandwidth. In order to achieve multi-Gb/s data rates, complex designs that equalize the channel are necessary. In addition, a high level of parallelism is central to sustaining bandwidth growth. Decision feedback equalization (DFE) is one of the most commonly employed techniques to overcome the limited bandwidth problem of the electrical channels. A linear and low-power summer is the central block of a DFE. Conventional approaches employ current-mode techniques to implement the summer, which require high power consumption. In order to achieve low-power operation we propose performing the summation in the charge domain. This approach enables a low-power and compact realization of the DFE as well as crosstalk cancellation. A prototype receiver was fabricated in 45nm SOI CMOS to validate the functionality of the proposed technique and was tested over channels with different levels of loss and coupling. Measurement results show that the receiver can equalize channels with maximum 21dB loss while consuming about 7.5mW from a 1.2V supply. We also introduce a compact, low-power transmitter employing passive equalization. The efficacy of the proposed technique is demonstrated through implementation of a prototype in 65nm CMOS. The design achieves up to 20Gb/s data rate while consuming less than 10mW.

An alternative to electrical signaling is to employ optical signaling for chip-to-chip interconnections, which offers low channel loss and cross-talk while providing high communication bandwidth. In this work we demonstrate the possibility of building compact and low-power optical receivers. A novel RC front-end is proposed that combines dynamic offset modulation and double-sampling techniques to eliminate the need for a short time constant at the input of the receiver. Unlike conventional designs, this receiver does not require a high-gain stage that runs at the data rate, making it suitable for low-power implementations. In addition, it allows time-division multiplexing to support very high data rates. A prototype was implemented in 65nm CMOS and achieved up to 24Gb/s with less than 0.4pJ/b power efficiency per channel. As the proposed design mainly employs digital blocks, it benefits greatly from technology scaling in terms of power and area saving.

As the technology scales, the number of transistors on the chip grows. This necessitates a corresponding increase in the bandwidth of the on-chip wires. In this dissertation, we take a close look at wire scaling and investigate its effect on wire performance metrics. We explore a novel on-chip communication link based on a double-sampling architecture and dynamic offset modulation technique that enables low power consumption and high data rates while achieving high bandwidth density in 28nm CMOS technology. The functionality of the link is demonstrated using different length minimum-pitch on-chip wires. Measurement results show that the link achieves up to 20Gb/s of data rate (12.5Gb/s/$\mu$m) with better than 136fJ/b of power efficiency.