Electrical, electrochemical, and optical characterization of ceria films

Acceptor-doped ceria has been recognized as a promising intermediate temperature solid oxide fuel cell electrode/electrolyte material. For practical implementation of ceria as a fuel cell electrolyte and for designing model experiments for electrochemical activity, it is necessary to fabricate thin films of ceria. Here, metal-organic chemical vapor deposition was carried out in a homemade reactor to grow ceria films for further electrical, electrochemical, and optical characterization. Doped/undoped ceria films are grown on single crystalline oxide wafers with/without Pt line pattern or Pt solid layer. Deposition conditions were varied to see the effect on the resultant film property. Recently, proton conduction in nanograined polycrystalline pellets of ceria drew much interest. Thickness-mode (through-plane, z-direction) electrical measurements were made to confirm the existence of proton conductivity and investigate the nature of the conduction pathway: exposed grain surfaces and parallel grain boundaries. Columnar structure presumably favors proton conduction, and we have found measurable proton conductivity enhancement. Electrochemical property of gas-columnar ceria interface on the hydrogen electrooxidation is studied by AC impedance spectroscopy. Isothermal gas composition dependence of the electrode resistance was studied to elucidate Sm doping level effect and microstructure effect. Significantly, preferred orientation is shown to affect the gas dependence and performance of the fuel cell anode. A hypothesis is proposed to explain the origin of this behavior. Lastly, an optical transmittance based methodology was developed to obtain reference refractive index and microstructural parameters (thickness, roughness, porosity) of ceria films via subsequent fitting procedure.

Electrical and optical interconnects for high-performance computing

Technology scaling has enabled drastic growth in the computational and storage capacity of integrated circuits (ICs). This constant growth drives an increasing demand for high-bandwidth communication between and within ICs. In this dissertation we focus on low-power solutions that address this demand. We divide communication links into three subcategories depending on the communication distance. Each category has a different set of challenges and requirements and is affected by CMOS technology scaling in a different manner. We start with short-range chip-to-chip links for board-level communication. Next we will discuss board-to-board links, which demand a longer communication range. Finally on-chip links with communication ranges of a few millimeters are discussed.

Electrical signaling is a natural choice for chip-to-chip communication due to efficient integration and low cost. IO data rates have increased to the point where electrical signaling is now limited by the channel bandwidth. In order to achieve multi-Gb/s data rates, complex designs that equalize the channel are necessary. In addition, a high level of parallelism is central to sustaining bandwidth growth. Decision feedback equalization (DFE) is one of the most commonly employed techniques to overcome the limited bandwidth problem of the electrical channels. A linear and low-power summer is the central block of a DFE. Conventional approaches employ current-mode techniques to implement the summer, which require high power consumption. In order to achieve low-power operation we propose performing the summation in the charge domain. This approach enables a low-power and compact realization of the DFE as well as crosstalk cancellation. A prototype receiver was fabricated in 45nm SOI CMOS to validate the functionality of the proposed technique and was tested over channels with different levels of loss and coupling. Measurement results show that the receiver can equalize channels with maximum 21dB loss while consuming about 7.5mW from a 1.2V supply. We also introduce a compact, low-power transmitter employing passive equalization. The efficacy of the proposed technique is demonstrated through implementation of a prototype in 65nm CMOS. The design achieves up to 20Gb/s data rate while consuming less than 10mW.

An alternative to electrical signaling is to employ optical signaling for chip-to-chip interconnections, which offers low channel loss and cross-talk while providing high communication bandwidth. In this work we demonstrate the possibility of building compact and low-power optical receivers. A novel RC front-end is proposed that combines dynamic offset modulation and double-sampling techniques to eliminate the need for a short time constant at the input of the receiver. Unlike conventional designs, this receiver does not require a high-gain stage that runs at the data rate, making it suitable for low-power implementations. In addition, it allows time-division multiplexing to support very high data rates. A prototype was implemented in 65nm CMOS and achieved up to 24Gb/s with less than 0.4pJ/b power efficiency per channel. As the proposed design mainly employs digital blocks, it benefits greatly from technology scaling in terms of power and area saving.

As the technology scales, the number of transistors on the chip grows. This necessitates a corresponding increase in the bandwidth of the on-chip wires. In this dissertation, we take a close look at wire scaling and investigate its effect on wire performance metrics. We explore a novel on-chip communication link based on a double-sampling architecture and dynamic offset modulation technique that enables low power consumption and high data rates while achieving high bandwidth density in 28nm CMOS technology. The functionality of the link is demonstrated using different length minimum-pitch on-chip wires. Measurement results show that the link achieves up to 20Gb/s of data rate (12.5Gb/s/$\mu$m) with better than 136fJ/b of power efficiency.

The electrical and magnetic properties of amorphous Pd-Cu-P alloys

The amorphous phases of the Pd-Cu-P system has been obtained using the technique of rapidly quenching from the liquid state. Broad maxima in the diffraction pattern were obtained in the X-ray diffraction studies which are indicative of a glass-like structure. The composition range over which the amorphous solid phase is retained for the Pd-Cu-P system is (Pd_100-xCu_x)₈₀P₂₀ with 10 ≤ x ≤ 50 and (Pd₆₅Cu₃₅)_100-yP_y with 15 ≤ y ≤ 24 and (Pd₆₀Cu₄₀)_100-yP_y with 15 ≤ y ≤ 24.

The electrical resistivity for the Pd-Cu-P alloys decreases with temperature as T² at low temperatures and as T at high temperatures up to the crystallization temperature. The structural scattering model of the resistivity proposed by Sinha and the spin-fluctuation resistivity model proposed by Hasegawa are re-examined in the light of the similarity of this result to the Pt-Ni-P and Pd-Ni-P systems. Objections are raised to these interpretations of the resistivity results and an alternate model is proposed consistent with the new results on Pd-Cu-P and the observation of similar effects in crystalline transition metal alloys. The observed negative temperature coefficients of resistivity in these amorphous alloys are thus interpreted as being due to the modification of the density of states with temperature through the electron-phonon interaction. The weak Pauli paramagnetism of the Pd-Cu-P, Pt-Ni-P and Pd-Ni-P alloys is interpreted as being modifications of the transition d-states as a result of the formation of strong transition metal-metalloid bonds rather than a large transfer of electrons from the glass former atoms (P in this case) to the d-band of the transition metal in a rigid band picture.

Electrical resistance and thermoelectric power of the metastable phases in tellurium-base alloys

By using techniques of rapid quenching from the melt, metastable phases have been obtained in ternary alloys which contain tellurium as a major component and two of the three noble metals (Cu, Ag, Au) as minor components. The metastable phases found in this investigation are either simple cubic or amorphous. The formation of the simple cubic phase is discussed. The electrical resistance and the thermoelectric power of the simple cubic alloy (Au₃₀Te₇₀) have been measured and interpreted in terms of atomic bondings. The semiconducting properties of a metastable amorphous alloy (Au₅Cu₂₅Te₇₀) have been measured. The experimental results are discussed in connection with a theoretical consideration of the validity of band theory in an amorphous solid. The existence of extrinsic conduction in an amorphous semiconductor is suggested by the result of electrical resistance and thermoelectric power measurements.

Electrical and optical investigations of beta-gallium oxide

An experimental investigation of the optical properties of β–gallium oxide has been carried out, covering the wavelength range 220-2500 nm.

The refractive index and birefringence have been determined to about ± 1% accuracy over the range 270-2500 nm, by the use of a technique based on the occurrence of fringes in the transmission of a thin sample due to multiple internal reflections in the sample (ie., the "channelled spectrum" of the sample.)

The optical absorption coefficient has been determined over the range 220 - 300 nm, which range spans the fundamental absorption edge of β – Ga₂O₃. Two techniques were used in the absorption coefficient determination: measurement of transmission of a thin sample, and measurement of photocurrent from a Schottky barrier formed on the surface of a sample. Absorption coefficient was measured over a range from 10 to greater than 10⁵, to an accuracy of better than ± 20%. The absorption edge was found to be strongly polarization-dependent.

Detailed analyses are presented of all three experimental techniques used. Experimentally determined values of the optical constants are presented in graphical form.