2 resultados para 3D gloves for footwear design

em CaltechTHESIS


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Recent developments in micro- and nanoscale 3D fabrication techniques have enabled the creation of materials with a controllable nanoarchitecture that can have structural features spanning 5 orders of magnitude from tens of nanometers to millimeters. These fabrication methods in conjunction with nanomaterial processing techniques permit a nearly unbounded design space through which new combinations of nanomaterials and architecture can be realized. In the course of this work, we designed, fabricated, and mechanically analyzed a wide range of nanoarchitected materials in the form of nanolattices made from polymer, composite, and hollow ceramic beams. Using a combination of two-photon lithography and atomic layer deposition, we fabricated samples with periodic and hierarchical architectures spanning densities over 4 orders of magnitude from ρ=0.3-300kg/m3 and with features as small as 5nm. Uniaxial compression and cyclic loading tests performed on different nanolattice topologies revealed a range of novel mechanical properties: the constituent nanoceramics used here have size-enhanced strengths that approach the theoretical limit of materials strength; hollow aluminum oxide (Al2O3) nanolattices exhibited ductile-like deformation and recovered nearly completely after compression to 50% strain when their wall thicknesses were reduced below 20nm due to the activation of shell buckling; hierarchical nanolattices exhibited enhanced recoverability and a near linear scaling of strength and stiffness with relative density, with E∝ρ1.04 and σy∝ρ1.17 for hollow Al2O3 samples; periodic rigid and non-rigid nanolattice topologies were tested and showed a nearly uniform scaling of strength and stiffness with relative density, marking a significant deviation from traditional theories on “bending” and “stretching” dominated cellular solids; and the mechanical behavior across all topologies was highly tunable and was observed to strongly correlate with the slenderness λ and the wall thickness-to-radius ratio t/a of the beams. These results demonstrate the potential of nanoarchitected materials to create new highly tunable mechanical metamaterials with previously unattainable properties.

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Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking.

In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy efficiency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The receiver sensitivity is measured to be -8.8dBm at 32Gb/s.

Next, on the optical transmitter side, three new techniques will be presented. First one is a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop. As a first proof of concept, a prototype has been fabricated and measured up to 10Gb/s. The second technique is thermal stabilization of micro-ring resonator modulators through direct measurement of temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. A prototype is fabricated and a closed-loop feedback system is demonstrated to operate at 20Gb/s in the presence of temperature fluctuations. The third technique is a switched-capacitor based pre-emphasis technique designed to extend the inherently low bandwidth of carrier injection micro-ring modulators. A measured prototype of the optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit based on the monolithic PTAT sensor consumes 0.29mW.

Lastly, a first-order frequency synthesizer that is suitable for high-speed on-chip clock generation will be discussed. The proposed design features an architecture combining an LC quadrature VCO, two sample-and-holds, a PI, digital coarse-tuning, and rotational frequency detection for fine-tuning. In addition to an electrical reference clock, as an extra feature, the prototype chip is capable of receiving a low jitter optical reference clock generated by a high-repetition-rate mode-locked laser. The output clock at 8GHz has an integrated RMS jitter of 490fs, peak-to-peak periodic jitter of 2.06ps, and total RMS jitter of 680fs. The reference spurs are measured to be –64.3dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.