Automatic Generation of Identical Routing Pairs for FPGA Implemented DPL Logic

Side Channel Attacks (SCAs) typically gather unintentional (side channel) physical leakages from running crypto-devices to reveal confidential data. Dual-rail Precharge Logic (DPL) is one of the most efficient countermeasures against power or EM side channel threats. This logic relies on the implementation of complementary rails to counterbalance the data-dependent variations of the leakage from dynamic behavior of the original circuit. However, the lack of flexibility of commercial FPGA design tools makes it quite difficult to obtain completely balanced routings between complementary networks. In this paper, a controllable repair mechanism to guarantee identical net pairs from two lines is presented: i. repairs the identical yet conflict nets after the duplication (copy & paste) from original rail to complementary rail, and ii. repairs the non-identical nets in off-the-stock DPL circuits; These rerouting steps are carried out starting from a placed and routed netlist using Xilinx Description Language (XDL). Low level XDL modifications have been completely automated using a set of APIs named RapidSmith. Experimental EM attacks show that the resistance level of an AES core after the automatic routing repair is increased in a factor of at least 3.5. Timing analyses further demonstrate that net delay differences between complementary networks are minimized significantly.

Passive neutron area monitor with pairs of TLDs as neutron detector

A passive neutron area monitor has been designed using Monte Carlo methods; the monitor is a polyethylene cylinder with pairs of thermoluminescent dosimeters (TLD600 and TLD700) as thermal neutron detector. The monitor was calibrated with a bare and a thermalzed 241AmBe neutron sources and its performance was evaluated measuring the ambient dose equivalent due to photoneutrons produced by a 15 MV linear accelerator for radiotherapy and the neutrons in the output of a TRIGA Mark III radial beam port.