Proposal of a three level complexity model for office automation

Office automation is one of the fields where the complexity related with technologies and working environments can be best shown. This is the starting point we have chosen to build up a theoretical model that shows us a scene quite different from the one traditionally considered. Through the development of the model, the levels of complexity associated with office automation and office environments have been identified, establishing a relationship between them. Thus, the model allows to state a general principle for sociotechnical design of office automation systems, comprising the ontological distinctions needed to properly evaluate each particular technology and its virtual contribution to office automation. From this fact comes the model's taxonomic ability to draw a global perspective of the state-of-art in office automation technologies.

An integrated framework for office information systems design and management

Information Technologies are complex and this is true even in the smallest piece of equipment. But this kind of complexity is nothing comparejwith the one that arises when this technology interact with society. Office Automation has been traditionally considered as a technical field but there is no way to find solutions from a technical point of view when the problems are primarily social in their origin. Technology management has to change its focus from a pure technical perspective to a sociotechnical point of view. To facilitate this change, we propose a model that allows a better understanding between the managerial and the technical world, offering a coherent, complete and integrated perspective of both. The base for this model is an unfolding of the complexity found in information Technologies and a matching of these complexities with several levels considered within the Office, Office Automation and Human Factors dimensions. Each one of these domains is studied trough a set of distinctions that create a new and powerful understanding of its reality. Using this model we build up a map of Office Automation to be use^not only by managers but also by technicians because the primaty advantage of such a framework is that it allows a comprehensive evaluation of technology without requhing extensive technical knowledge. Thus, the model can be seen as principle for design and diagnosis of Office Automation and as a common reference for managers and specialist avoiding the severe limitations arising from the language used by the last

Low-Cost Radar-Based Target Identification Prototype using an Expert System

Smart and green cities are hot topics in current research because people are becoming more conscious about their impact on the environment and the sustainability of their cities as the population increases. Many researchers are searching for mechanisms that can reduce power consumption and pollution in the city environment. This paper addresses the issue of public lighting and how it can be improved in order to achieve a more energy efficient city. This work is focused on making the process of turning the streetlights on and off more intelligent so that they consume less power and cause less light pollution. The proposed solution is comprised of a radar device and an expert system implemented on a low-cost platform based on a DSP. By analyzing the radar echo in both the frequency and time domains, the system is able to detect and identify objects moving in front of it. This information is used to decide whether or not the streetlight should be turned on. Experimental results show that the proposed system can provide hit rates over 80%, promising a good performance. In addition, the proposed solution could be useful in kind of other applications such as intelligent security and surveillance systems and home automation.

An ontology-driven communication architecture for spontaneous interoperability in Home Automation systems

Current solutions to the interoperability problem in Home Automation systems are based on a priori agreements where protocols are standardized and later integrated through specific gateways. In this regards, spontaneous interoperability, or the ability to integrate new devices into the system with minimum planning in advance, is still considered a major challenge that requires new models of connectivity. In this paper we present an ontology-driven communication architecture whose main contribution is that it facilitates spontaneous interoperability at system model level by means of semantic integration. The architecture has been validated through a prototype and the main challenges for achieving complete spontaneous interoperability are also evaluated.

HALA!'s White Paper. Towards Higher Levels of Automation in ATM

��� Objectives of HALA! ��� Main Activities ��� HALA! Magement Team ��� Participants ��� Intended Audience ��� Heritage in ATM and Automation ��� The new paradigm shift in Automation in ATM ��� Overall system performance as main driver for ATM Automation ��� The three interdependent dimensions for the paradigm change. ��� New roles assignment based on : ��� ���best time��� ��� ���decision place��� ��� ���best player��� ��� HALA! main research areas

Experiments in abstract interpretation-based code certification for pervasive systems

Proof carrying code (PCC) is a general is originally a roof in ��rst-order logic of certain vermethodology for certifying that the execution of an un- ification onditions and the checking process involves trusted mobile code is safe. The baste idea is that the ensuring that the certif��cate is indeed a valid ��rst-order code supplier attaches a certif��cate to the mobile code proof. which the consumer checks in order to ensure that the The main practical dif��culty of PCC techniques is in code is indeed safe. The potential benefit is that the generating safety certi��eates which at the same time: i) consumer's task is reduced from the level of proving to allow expressing interesting safety properties, ii) can be the level of checking. Recently, the abstract interpre- generated automatically and, iii) are easy and efficient tation techniques developed, in logic programming have to check. In [1], the abstract interpretation techniques been proposed as a basis for PCC. This extended ab- [5] developed in logic programming1 are proposed as stract reports on experiments which illustrate several is- a basis for PCC. They offer a number of advantages sues involved in abstract interpretation-based certifica- for dealing with the aforementioned issues. In particution. First, we describe the implementation of our sys- lar, the xpressiveness of existing abstract domains will tem in the context of CiaoPP: the preprocessor of the be implicitly available in abstract interpretation-based Ciao multi-paradigm programming system. Then, by code certification to de��ne a wide range of safety propermeans of some experiments, we show how code certifi- ties. Furthermore, the approach inherits the automation cati��n is aided in the implementation of the framework. and inference power of the abstract interpretation en- Finally, we discuss the application of our method within gines used in (Constraint) Logic Programming, (C)LP. the ��rea, of pervasive systems

Data Processing Modeling in Decision Support Systems.

Due to the advancement of both, information technology in general, and databases in particular; data storage devices are becoming cheaper and data processing speed is increasing. As result of this, organizations tend to store large volumes of data holding great potential information. Decision Support Systems, DSS try to use the stored data to obtain valuable information for organizations. In this paper, we use both data models and use cases to represent the functionality of data processing in DSS following Software Engineering processes. We propose a methodology to develop DSS in the Analysis phase, respective of data processing modeling. We have used, as a starting point, a data model adapted to the semantics involved in multidimensional databases or data warehouses, DW. Also, we have taken an algorithm that provides us with all the possible ways to automatically cross check multidimensional model data. Using the aforementioned, we propose diagrams and descriptions of use cases, which can be considered as patterns representing the DSS functionality, in regard to DW data processing, DW on which DSS are based. We highlight the reusability and automation benefits that this can be achieved, and we think this study can serve as a guide in the development of DSS.

Functional modeling applied to HAZOP automation

In this paper we present a new tool to perform guided HAZOP analyses. This tool uses a functional model of the process that merges its functional and its structural information in a natural way. The functional modeling technique used is called D-higraphs. This tool solves some of the problems and drawbacks of other existing methodologies for the automation of HAZOPs. The applicability and easy understanding of the proposed methodology is shown in an industrial case.

Gesti��n de pruebas para equipos de v��deo

Desde hace ya muchos a��os, uno de los servicios de telecomunicaciones m��s demandado por los espa��oles ha sido la televisi��n de pago, complementando y ampliando la oferta de contenidos audiovisuales que habitualmente son ofrecidos de manera gratuita por la televisi��n anal��gica y recientemente por la televisi��n digital terrestre o TDT. Estos servicios de video, han sido tradicionalmente ofrecidos por operadores sat��lites, operadores de cable u otros operadores de telecomunicaciones con los que a trav��s de una conexi��n de datos (ADSL, VDSL o fibra ��ptica), ofrec��an sus contenidos a trav��s de IP. La propia evoluci��n y mejora de la tecnolog��a utilizada para la emisi��n de contenidos sobre IP, ha permitido que a d��a de hoy, la televisi��n se conciba como un servicio Over The Top (OTT) ajeno al medio de transmisi��n, permitiendo a cualquier agente, distribuir sus contenidos audiovisuales de manera sencilla y a todos sus clientes en todas las partes del mundo; siendo solamente necesario disponer de una conexi��n a internet. De esta manera, el proyecto desarrollado va a girar en torno a la herramienta StormTest de la empresa S3Group, comprada por CENTUM Solutions (empresa especializada en ofrecer servicio de ingenier��a para sistema de comunicaciones, control e inteligencia de se��al) con el objetivo de satisfacer las necesidades de sus clientes y con la que en definitiva se ha contado para la realizaci��n de este proyecto. El principal objetivo de este proyecto es la definici��n e implementaci��n de un banco de pruebas que permita optimizar los procesos de validaci��n t��cnica, mejorando los tiempos de ejecuci��n y concentrando la actividad de los ingenieros en tareas de mayor valor. Para la realizaci��n de este proyecto, se han fijado diversos objetivos necesarios para el desarrollo de este tipo de actividades. Los principales son los siguientes: ��� An��lisis de la problem��tica actual: donde en los procesos de aceptaci��n t��cnica se dedica muchas horas de trabajo para la realizaci��n de pruebas repetitivas y de poco valor las cuales se pueden automatizar por herramientas existentes en el mercado. ��� B��squeda y selecci��n de una herramienta que satisfaga las necesidades de pruebas. ��� Instalaci��n en los laboratorios. ��� Configuraci��n y adaptaci��n de la herramienta a las necesidades y proyectos espec��ficos. Con todo ello, este proyecto cubrir�� los siguientes logros: ��� Reducir los tiempos de ejecuci��n de las campa��as de pruebas, gracias a la automatizaci��n de gran parte ellas. ��� Realizar medidas de calidad subjetiva y objetiva complejas, imposibles de ejecutar a trav��s de las personas. Mejorar y automatizar los sistemas de reporte de resultados. Abstract: Many years ago, one of the telecommunications services most demanded in Spain has been pay television, complementing and extending the offer of audiovisual content which are usually offered for free by analog tv and recently by digital terrestrial televisi��n or TDT. These video services, have been traditionally offered by satellite operators, cable operators or other telecommunications operators that through a data connection (ADSL,VDSL or fiber optic), offered its content over IP. The evolution and improvement of the technology used for broadcasting over IP, has allowed that to date, television is conceived as a service Over The Top (OTT), not dependent on the transmission medium, allowing any agent to distribute audiovisual content in a very simple way and to all its customers in all parts of the world; being only necessary to have an decent internet connection. In this way, the project will have relation with S3Group���s StormTest tool, bought by CENTUM Solutions (company specialized in engineering services for communications, control and signal intelligence system) with the aim of satisfying the needs of its customers and which ultimately has counted for the realization of this project. The main objective of this project is the definition and implementation of a test bench that allows to optimize the processes of technical validation, improving execution times and concentrating the activities of engineers on higher value tasks. For the realization of this project, it has been defined several objectives necessary for the development of this type of activity. The most important tones are listed below: ��� Analysis of the current situation: where in technical acceptance processes it is dedicated many hours of work for the completion of repetitive testing and without value which can be automated by tools available on the market ��� Search and selection of a tool that meets the needs of testing. ��� Installation on the laboratories. ��� Configuration and customization of the tool to specific projects. With all this, this project will cover the following achievements: Reduce the execution time of the testing campaigns, thanks to the automation of many of them. ��� Measurements of subjective and objective quality tests, impossible to run with engineers (due to subjective perception). Improve and automate reporting of results systems

Towards��model-driven engineering for mixed-criticality systems: multiPARTES approach

Mixed criticality systems emerges as a suitable solution for dealing with the complexity, performance and costs of future embedded and dependable systems. However, this paradigm adds additional complexity to their development. This paper proposes an approach for dealing with this scenario that relies on hardware virtualization and Model-Driven Engineering (MDE). Hardware virtualization ensures isolation between subsystems with different criticality levels. MDE is intended to bridge the gap between design issues and partitioning concerns. MDE tooling will enhance the functional models by annotating partitioning and extra-functional properties. System partitioning and subsystems allocation will be generated with a high degree of automation. System configuration will be validated for ensuring that the resources assigned to a partition are sufficient for executing the allocated software components and that time requirements are met.

Implementation of a building automation system based on semantic modeling

This paper presents an Ontology-Based multi-technology platform designed to avoid some issues of Building Automation Systems. The platform allows the integration of several building automation protocols, eases the development and implementation of different kinds of services and allows sharing information related to the infrastructure and facilities within a building. The system has been implemented and tested in the Energy Efficiency Research Facility at CeDInt-UPM.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en t��cnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en ingl��s), que han sido propuestas dentro del campo de investigaci��n acad��mica desde hace 17 a��os. Las investigaciones relacionadas han experimentado un notable crecimiento en las ��ltimas d��cadas, mientras que los dise��os enfocados en la protecci��n s��lida y eficaz contra dichos ataques a��n se mantienen como un tema de investigaci��n abierto, en el que se necesitan iniciativas m��s confiables para la protecci��n de la informaci��n persona de empresa y de datos nacionales. El primer uso documentado de codificaci��n secreta se remonta a alrededor de 1700 B.C., cuando los jerogl��ficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la informaci��n siempre ha supuesto un factor clave en la transmisi��n de datos relacionados con inteligencia diplom��tica o militar. Debido a la evoluci��n r��pida de las t��cnicas modernas de comunicaci��n, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisi��n a trav��s de cables sin seguridad o medios inal��mbricos. Debido a las restricciones de potencia de c��lculo antes de la era del ordenador, la t��cnica de cifrado simple era un m��todo m��s que suficiente para ocultar la informaci��n. Sin embargo, algunas vulnerabilidades algor��tmicas pueden ser explotadas para restaurar la regla de codificaci��n sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el ��rea de la criptograf��a, con el fin de proteger el sistema de informaci��n ante sofisticados algoritmos. Con la invenci��n de los ordenadores se ha acelerado en gran medida la implementaci��n de criptograf��a segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computaci��n altamente reforzadas. Igualmente, sofisticados cripto-an��lisis han impulsado las tecnolog��as de computaci��n. Hoy en d��a, el mundo de la informaci��n ha estado involucrado con el campo de la criptograf��a, enfocada a proteger cualquier campo a trav��s de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificaci��n optimizada de teor��as matem��ticas modernas y pr��cticas eficaces de hardware, siendo posible su implementaci��n en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales m��tricas de conducci��n en el dise��o electr��nico, con el objetivo de promover la fabricaci��n de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementaci��n pr��ctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de an��lisis. Sin embargo, algunas cr��ticas sobre los algoritmos criptogr��ficos te��ricamente seguros surgieron casi inmediatamente despu��s de este descubrimiento. En este sentido, los circuitos digitales consisten t��picamente en un gran n��mero de celdas l��gicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricaci��n. La l��gica de los circuitos se realiza en funci��n de las innumerables conmutaciones de estas c��lulas. Este mecanismo provoca inevitablemente cierta emanaci��n f��sica especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptograf��a de claves), analizar la arquitectura l��gica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparaci��n de correlaci��n entre la cantidad de fuga estimada y las fugas medidas de forma real, informaci��n confidencial puede ser reconstruida en mucho menos tiempo y computaci��n. Para ser precisos, SCA b��sicamente cubre una amplia gama de tipos de ataques, como los an��lisis de consumo de energ��a y radiaci��n ElectroMagn��tica (EM). Ambos se basan en an��lisis estad��stico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no est��n intr��nsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementaci��n de circuitos integrar medidas que permitan camuflar las fugas a trav��s de "canales laterales". Las medidas contra SCA est��n evolucionando junto con el desarrollo de nuevas t��cnicas de ataque, as�� como la continua mejora de los dispositivos electr��nicos. Las caracter��sticas f��sicas requieren contramedidas sobre la capa f��sica, que generalmente se pueden clasificar en soluciones intr��nsecas y extr��nsecas. Contramedidas extr��nsecas se ejecutan para confundir la fuente de ataque mediante la integraci��n de ruido o mala alineaci��n de la actividad interna. Comparativamente, las contramedidas intr��nsecas est��n integradas en el propio algoritmo, para modificar la aplicaci��n con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultaci��n y Enmascaramiento son dos t��cnicas t��picas incluidas en esta categor��a. Concretamente, el enmascaramiento se aplica a nivel algor��tmico, para alterar los datos intermedios sensibles con una m��scara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptograf��as modernas son dif��ciles de enmascarar. Dicho m��todo de ocultaci��n, que ha sido verificado como una soluci��n efectiva, comprende principalmente la codificaci��n en doble carril, que est�� ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, adem��s de la descripci��n de las metodolog��as de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la l��gica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel l��gico. Una caracter��stica de SCA reside en el formato de las fuentes de fugas. Un t��pico ataque de canal lateral se refiere al an��lisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades par��sitas son las fuentes esenciales de fugas. Por lo tanto, una l��gica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas l��gicas b��sicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la l��gica desde un nivel m��s alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones cl��sicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementaci��n de un esquema de dise��o personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el dise��o y la implementaci��n de una l��gica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener din��micamente el equilibrio de las fugas en las capas inferiores; II. Esta l��gica explota las caracter��sticas de la arquitectura de las FPGAs, para reducir al m��nimo el gasto de recursos en la implementaci��n; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo gen��rico de dise��o sobre FPGAs, con el fin de manipular los circuitos de forma autom��tica. El kit de herramientas de dise��o autom��tico es compatible con la l��gica de doble carril propuesta, para facilitar la aplicaci��n pr��ctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodolog��a y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho m��s r��gidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementaci��n y reparaci��n de l��gica de doble carril gen��rica. La viabilidad de las soluciones propuestas es validada mediante la selecci��n de algoritmos criptogr��ficos ampliamente utilizados, y su evaluaci��n exhaustiva en comparaci��n con soluciones anteriores. Todas las propuestas est��n respaldadas eficazmente a trav��s de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigaci��n tiene la intenci��n de cerrar la brecha entre las barreras de implementaci��n y la aplicaci��n efectiva de l��gica de doble carril. En esencia, a lo largo de esta tesis se describir�� un conjunto de herramientas de implementaci��n para FPGAs que se han desarrollado para trabajar junto con el flujo de dise��o gen��rico de las mismas, con el fin de lograr crear de forma innovadora la l��gica de doble carril. Un nuevo enfoque en el ��mbito de la seguridad en el cifrado se propone para obtener personalizaci��n, automatizaci��n y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigaci��n se resumen brevemente a continuaci��n: ������L��gica de Precharge Absorbed-DPL logic: El uso de la conversi��n de netlist para reservar LUTs libres para ejecutar la se��al de precharge y Ex en una l��gica DPL. ������Posicionamiento entrelazado Row-crossed con pares id��nticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medici��n EM selectiva y mitigar los impactos de las variaciones de proceso. ������Ejecuci��n personalizada y herramientas de conversi��n autom��tica para la generaci��n de redes id��nticas para la l��gica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asim��tricas. (c) Para ser utilizado en otras l��gicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. ������Plataforma CPA de pruebas personalizadas para el an��lisis de EM y potencia, incluyendo la construcci��n de dicha plataforma, el m��todo de medici��n y an��lisis de los ataques. ������An��lisis de tiempos para cuantificar los niveles de seguridad. ������Divisi��n de Seguridad en la conversi��n parcial de un sistema de cifrado complejo para reducir los costes de la protecci��n. ������Prueba de concepto de un sistema de calefacci��n auto-adaptativo para mitigar los impactos el��ctricos debido a la variaci��n del proceso de silicio de manera din��mica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuaci��n: En el cap��tulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos b��sicos de teor��a de modelos de an��lisis, adem��s de la implementaci��n de la plataforma y la ejecuci��n de los ataques. En el cap��tulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Adem��s de ello, en este cap��tulo se propone una l��gica en doble carril compacta y segura como contribuci��n de gran relevancia, as�� como tambi��n se presentar�� la transformaci��n l��gica basada en un dise��o a nivel de puerta. Por otra parte, en el Cap��tulo 3 se abordan los desaf��os relacionados con la implementaci��n de l��gica en doble carril gen��rica. As�� mismo, se describir�� un flujo de dise��o personalizado para resolver los problemas de aplicaci��n junto con una herramienta de desarrollo autom��tico de aplicaciones propuesta, para mitigar las barreras de dise��o y facilitar los procesos. En el cap��tulo 4 se describe de forma detallada la elaboraci��n e implementaci��n de las herramientas propuestas. Por otra parte, la verificaci��n y validaciones de seguridad de la l��gica propuesta, as�� como un sofisticado experimento de verificaci��n de la seguridad del rutado, se describen en el cap��tulo 5. Por ��ltimo, un resumen de las conclusiones de la tesis y las perspectivas como l��neas futuras se incluyen en el cap��tulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada cap��tulo se describe de forma m��s detallada a continuaci��n: En el cap��tulo 1 se introduce plataforma de implementaci��n hardware adem��s las teor��as b��sicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura gen��rica y las caracter��sticas de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un m��dulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los m��todos de canal lateral, que permiten revelar las fugas de disipaci��n correlacionadas con los comportamientos internos; y el m��todo para recuperar esta relaci��n entre las fluctuaciones f��sicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del cap��tulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protecci��n de la compensaci��n din��mica de la l��gica gen��rica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripci��n de los elementos compensados a nivel de puerta. En segundo lugar, la l��gica PA-DPL es propuesta como aportaci��n original, detallando el protocolo de la l��gica y un caso de aplicaci��n. En tercer lugar, dos flujos de dise��o personalizados se muestran para realizar la conversi��n de doble carril. Junto con ello, se aclaran las definiciones t��cnicas relacionadas con la manipulaci��n por encima de la netlist a nivel de LUT. Finalmente, una breve discusi��n sobre el proceso global se aborda en la parte final del cap��tulo. El Cap��tulo 3 estudia los principales retos durante la implementaci��n de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantaci��n a trav��s de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos par��sitos, sesgo tecnol��gico y la viabilidad de implementaci��n. De acuerdo con estas elaboraciones, se plantean dos problemas: C��mo implementar la l��gica propuesta sin penalizar los niveles de seguridad, y c��mo manipular un gran n��mero de celdas y automatizar el proceso. El PA-DPL propuesto en el cap��tulo 2 se valida con una serie de iniciativas, desde caracter��sticas estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los m��todos de aplicaci��n tales como las herramientas de personalizaci��n y automatizaci��n de EDA. Por otra parte, un sistema de calefacci��n auto-adaptativo es representado y aplicado a una l��gica de doble n��cleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variaci��n del proceso durante la operaci��n en tiempo real. El cap��tulo 4 se centra en los detalles de la implementaci��n del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la l��gica de circuito post P&R ncd (una versi��n binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y raz��n de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detecci��n de enrutamiento y los enfoques para la reparaci��n. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente id��nticos para la l��gica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este cap��tulo particularmente especifica las bases t��cnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El cap��tulo 5 se enfoca en la aplicaci��n de los casos de estudio para la validaci��n de los grados de seguridad de la l��gica propuesta. Se discuten los problemas t��cnicos detallados durante la ejecuci��n y algunas nuevas t��cnicas de implementaci��n. (a) Se discute el impacto en el proceso de posicionamiento de la l��gica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementaci��n, tomando en cuenta la optimizaci��n global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparaci��n optimizados; (b) las validaciones de seguridad se realizan con los m��todos de correlaci��n y an��lisis de tiempo; (c) Una t��ctica asint��tica se aplica a un n��cleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre m��tricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacci��n auto-adaptativa sobre la variaci��n del proceso son mostrados; (e) Se introduce una aplicaci��n pr��ctica de las herramientas para un dise��o de cifrado completa. Cap��tulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por ��ltimo, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilizaci��n de las contribuciones de esta tesis a un alcance m��s all�� de los dominios de la criptograf��a en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: ������Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. ������A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. ������Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. ���������Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. ������A timing analysis based method for quantifying the security grades. ������A methodology of security partitions of complex crypto systems for reducing the protection cost. ������A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Caracterizaci��n de Sistemas intensivos en Software desde un punto de vista de innovaci��n=Characterizing Software-intensive Systems from the innovation point of view

La innovaci��n en Sistemas Intesivos en Software est�� alcanzando relevancia por m��ltiples razones: el software est�� presente en sectores como autom��vil, tel��fonos m��viles o salud. Las empresas necesitan conocer aquellos factores que afectan a la innovaci��n para incrementar las probabilidades de ��xito en el desarrollo de sus productos y, la evaluaci��n de productos sofware es un mecanismo potente para capturar este conocimiento. En consecuencia, las empresas necesitan evaluar sus productos desde la perpectiva de innovaci��n para reducir la distancia entre los productos desarrollados y el mercado. Esto es incluso m��s relevante en el caso de los productos intensivos en software, donde el tiempo real, la oportunidad, complejidad, interoperabilidad, capacidad de respuesta y compartci��n de recursos son caracter��sticas cr��ticas de los nuevos sistemas. La evaluaci��n de la innovaci��n de productos ya ha sido estudiada y se han definido algunos esquemas de evaluaci��n pero no son espec��ficos para Sistemas intensivos en Sofwtare; adem��s, no se ha alcanzado consenso en los factores ni el procedimiento de evaluaci��n. Por lo tanto, tiene sentido trabajar en la definici��n de un marco de evaluaci��n de innovaci��n enfocado a Sistemas intesivos en Software. Esta tesis identifica los elementos necesarios para construir in marco para la evaluaci��n de de Sistemas intensivos en Software desde el punto de vista de la innovaci��n. Se han identificado dos componentes como partes del marco de evaluaci��n: un modelo de referencia y una herramienta adaptativa y personalizable para la realizaci��n de la evaluaci��n y posicionamiento de la innovaci��n. El modelo de referencia est�� compuesto por cuatro elementos principales que caracterizan la evaluaci��n de innovaci��n de productos: los conceptos, modelos de innovaci��n, cuestionarios de evaluaci��n y la evaluaci��n de productos. El modelo de referencia aporta las bases para definir instancias de los modelos de evaluaci��n de innovaci��n de productos que pueden se evaluados y posicionados en la herramienta a trav��s de cuestionarios y que de forma automatizada aporta los resultados de la evaluaci��n y el posicionamiento respecto a la innovaci��n de producto. El modelo de referencia ha sido rigurosamente construido aplicando modelado conceptual e integraci��n de vistas junto con la aplicaci��n de m��todos cualitativos de investigaci��n. La herramienta ha sido utilizada para evaluar productos como Skype a trav��s de la instanciaci��n del modelo de referencia. ABSTRACT Innovation in Software intensive Systems is becoming relevant for several reasons: software is present embedded in many sectors like automotive, robotics, mobile phones or heath care. Firms need to have knowledge about factors affecting the innovation to increase the probability of success in their product development and the assessment of innovation in software products is a powerful mechanism to capture this knowledge. Therefore, companies need to assess products from an innovation perspective to reduce the gap between their developed products and the market. This is even more relevant in the case of SiSs, where real time, timeliness, complexity, interoperability, reactivity, and resource sharing are critical features of a new system. Many authors have analysed product innovation assessment and some schemas have been developed but they are not specific to SiSs; in addition, there is no consensus about the factors or the procedures for performing an assessment. Therefore, it has sense to work in the definition of a customized software product innovation evaluation framework. This thesis identifies the elements needed to build a framework to assess software products from the innovation perspective. Two components have been identified as part of the framework to assess Software intensive Systems from the innovation perspective: a reference-model and an adaptive and customizable tool to perform the assessment and to position product innovation. The reference-model is composed by four main elements characterizing product innovation assessment: concepts, innovation models, assessment questionnaires and product assessment. The reference model provides the umbrella to define instances of product innovation assessment models that can be assessed and positioned through questionnaires in the proposed tool that also provides automation in the assessment and positioning of innovation. The reference-model has been rigorously built by applying conceptual modelling and view integration integrated with qualitative research methods. The tool has been used to assess products like Skype through models instantiated from the reference-model.

Enhancing regression models for complex systems using evolutionary techniques for feature engineering

This work proposes an automatic methodology for modeling complex systems. Our methodology is based on the combination of Grammatical Evolution and classical regression to obtain an optimal set of features that take part of a linear and convex model. This technique provides both Feature Engineering and Symbolic Regression in order to infer accurate models with no effort or designer's expertise requirements. As advanced Cloud services are becoming mainstream, the contribution of data centers in the overall power consumption of modern cities is growing dramatically. These facilities consume from 10 to 100 times more power per square foot than typical office buildings. Modeling the power consumption for these infrastructures is crucial to anticipate the effects of aggressive optimization policies, but accurate and fast power modeling is a complex challenge for high-end servers not yet satisfied by analytical approaches. For this case study, our methodology minimizes error in power prediction. This work has been tested using real Cloud applications resulting on an average error in power estimation of 3.98%. Our work improves the possibilities of deriving Cloud energy efficient policies in Cloud data centers being applicable to other computing environments with similar characteristics.

The Use of Patents to Assess National Innovation Systems: Evidences from Spanish Biotechnology

Spain���s economy recorded a high rate of growth from the mid-1990s onwards. At the same time, the resources allocated to Research and Development (R&D) grew at a much faster pace than in other European Union (EU) countries. Spain���s growth recorded an average rate of 2.93% from the early 1990s to 2004. Over the same period, the average growth in the EU was 0.46%. This circumstance, together with several sound policy decisions implemented between 2004 and 2009, ushered in a ���golden age of Spanish biotechnology���. In terms of the national patent licenses issued by the Spanish Patent and Trademark Office (SPTO) between 2004 and 2009, the number in biotechnology grew from 84 to 151. However, the current economic situation in Spain, along with a series of political decisions taken over the past two or three years to cut spending on R&D, predicts a sharp downturn in the performance of Spanish biotechnology. This scenario makes Spain one of the best places to study the successes and failures of the management of science and allows transfer this experience to the other international regions. We need to analyze the influence of political decisions as a major factor with a bearing on the quality of science. Using patents as an indicator of scientific development, this paper analyzes the evolution of the biotechnology sector in Spain and its relationship with scientific policy and the management of R&D.