Soft solution fluorine-free synthesis of anatase nanoparticles with tailored morphology

TiO2 nanoparticles with tailored morphology have been synthesized under exceptionally soft conditions. The strategy is based on the use of a non-aqueous alcoholic reaction medium in which water traces, coming either from the air (atmospheric water) or from an ethanol–water azeotropic mixture (ethanol 96%), are incorporated in order to accelerate hydrolysis of the Ti–precursor. Moreover, organic surfactants have been used as capping agents so as to tailor crystal growth in certain preferential directions. Combinations of oleic acid and oleylamine, which lead to the formation of another surfactant, dioleamide, are employed instead of fluorine-based compounds, thus increasing the sustainability of the process. As a result, TiO2 nanostructured hierarchical microspheres and individual nanoparticles with exposed high-energy facets can be obtained at atmospheric pressure and temperatures as low as 78 °C.

Recrystallization of amorphous nano-tracks and uniform layers generated by swift-ion-beam irradiation in lithium niobate.

The thermal annealing of amorphous tracks of nanometer-size diameter generated in lithium niobate (LiNbO3) by Bromine ions at 45 MeV, i.e., in the electronic stopping regime, has been investigated by RBS/C spectrometry in the temperature range from 250°C to 350°C. Relatively low fluences have been used (<1012 cm−2) to produce isolated tracks. However, the possible effect of track overlapping has been investigated by varying the fluence between 3×1011 cm−2 and 1012 cm−2. The annealing process follows a two-step kinetics. In a first stage (I) the track radius decreases linearly with the annealing time. It obeys an Arrhenius-type dependence on annealing temperature with activation energy around 1.5 eV. The second stage (II) operates after the track radius has decreased down to around 2.5 nm and shows a much lower radial velocity. The data for stage I appear consistent with a solid-phase epitaxial process that yields a constant recrystallization rate at the amorphous-crystalline boundary. HRTEM has been used to monitor the existence and the size of the annealed isolated tracks in the second stage. On the other hand, the thermal annealing of homogeneous (buried) amorphous layers has been investigated within the same temperature range, on samples irradiated with Fluorine at 20 MeV and fluences of ∼1014 cm−2. Optical techniques are very suitable for this case and have been used to monitor the recrystallization of the layers. The annealing process induces a displacement of the crystalline-amorphous boundary that is also linear with annealing time, and the recrystallization rates are consistent with those measured for tracks. The comparison of these data with those previously obtained for the heavily damaged (amorphous) layers produced by elastic nuclear collisions is summarily discussed.

Fabrication and characterization at high temperature of AlGaN/GaN enhancement HEMTs

Enhancement-mode (E-mode) high electron mobility transistors (HEMTs) based on a standard AlGaN/GaN heterostructure have been fabricated using two different methods: 19F implantation and fluorine-based plasma treatment. The need of a thermal annealing after both treatments has been proven in order to restore the ID and gm levels. DC characterization at high temperature has demonstrated that ID and gm decrease reversibly due to the reduction of the electron mobility and the drift velocity. Pulsed measurements (state period and variable pulse width) have been performed to study the self-heating effects.

Technology and characterization of GaN-HEMTs devices: high temperature and trapping effects

Los transistores de alta movilidad electrónica basados en GaN han sido objeto de una extensa investigación ya que tanto el GaN como sus aleaciones presentan unas excelentes propiedades eléctricas (alta movilidad, elevada concentración de portadores y campo eléctrico crítico alto). Aunque recientemente se han incluido en algunas aplicaciones comerciales, su expansión en el mercado está condicionada a la mejora de varios asuntos relacionados con su rendimiento y habilidad. Durante esta tesis se han abordado algunos de estos aspectos relevantes; por ejemplo, la fabricación de enhancement mode HEMTs, su funcionamiento a alta temperatura, el auto calentamiento y el atrapamiento de carga. Los HEMTs normalmente apagado o enhancement mode han atraído la atención de la comunidad científica dedicada al desarrollo de circuitos amplificadores y conmutadores de potencia, ya que su utilización disminuiría significativamente el consumo de potencia; además de requerir solamente una tensión de alimentación negativa, y reducir la complejidad del circuito y su coste. Durante esta tesis se han evaluado varias técnicas utilizadas para la fabricación de estos dispositivos: el ataque húmedo para conseguir el gate-recess en heterostructuras de InAl(Ga)N/GaN; y tratamientos basados en flúor (plasma CF4 e implantación de F) de la zona debajo de la puerta. Se han llevado a cabo ataques húmedos en heteroestructuras de InAl(Ga)N crecidas sobre sustratos de Si, SiC y zafiro. El ataque completo de la barrera se consiguió únicamente en las muestras con sustrato de Si. Por lo tanto, se puede deducir que la velocidad de ataque depende de la densidad de dislocaciones presentes en la estructura, ya que el Si presenta un peor ajuste del parámetro de red con el GaN. En relación a los tratamientos basados en flúor, se ha comprobado que es necesario realizar un recocido térmico después de la fabricación de la puerta para recuperar la heteroestructura de los daños causados durante dichos tratamientos. Además, el estudio de la evolución de la tensión umbral con el tiempo de recocido ha demostrado que en los HEMTs tratados con plasma ésta tiende a valores más negativos al aumentar el tiempo de recocido. Por el contrario, la tensión umbral de los HEMTs implantados se desplaza hacia valores más positivos, lo cual se atribuye a la introducción de iones de flúor a niveles más profundos de la heterostructura. Los transistores fabricados con plasma presentaron mejor funcionamiento en DC a temperatura ambiente que los implantados. Su estudio a alta temperatura ha revelado una reducción del funcionamiento de todos los dispositivos con la temperatura. Los valores iniciales de corriente de drenador y de transconductancia medidos a temperatura ambiente se recuperaron después del ciclo térmico, por lo que se deduce que dichos efectos térmicos son reversibles. Se han estudiado varios aspectos relacionados con el funcionamiento de los HEMTs a diferentes temperaturas. En primer lugar, se han evaluado las prestaciones de dispositivos de AlGaN/GaN sobre sustrato de Si con diferentes caps: GaN, in situ SiN e in situ SiN/GaN, desde 25 K hasta 550 K. Los transistores con in situ SiN presentaron los valores más altos de corriente drenador, transconductancia, y los valores más bajos de resistencia-ON, así como las mejores características en corte. Además, se ha confirmado que dichos dispositivos presentan gran robustez frente al estrés térmico. En segundo lugar, se ha estudiado el funcionamiento de transistores de InAlN/GaN con diferentes diseños y geometrías. Dichos dispositivos presentaron una reducción casi lineal de los parámetros en DC en el rango de temperaturas de 25°C hasta 225°C. Esto se debe principalmente a la dependencia térmica de la movilidad electrónica, y también a la reducción de la drift velocity con la temperatura. Además, los transistores con mayores longitudes de puerta mostraron una mayor reducción de su funcionamiento, lo cual se atribuye a que la drift velocity disminuye más considerablemente con la temperatura cuando el campo eléctrico es pequeño. De manera similar, al aumentar la distancia entre la puerta y el drenador, el funcionamiento del HEMT presentó una mayor reducción con la temperatura. Por lo tanto, se puede deducir que la degradación del funcionamiento de los HEMTs causada por el aumento de la temperatura depende tanto de la longitud de la puerta como de la distancia entre la puerta y el drenador. Por otra parte, la alta densidad de potencia generada en la región activa de estos transistores conlleva el auto calentamiento de los mismos por efecto Joule, lo cual puede degradar su funcionamiento y Habilidad. Durante esta tesis se ha desarrollado un simple método para la determinación de la temperatura del canal basado en medidas eléctricas. La aplicación de dicha técnica junto con la realización de simulaciones electrotérmicas han posibilitado el estudio de varios aspectos relacionados con el autocalentamiento. Por ejemplo, se han evaluado sus efectos en dispositivos sobre Si, SiC, y zafiro. Los transistores sobre SiC han mostrado menores efectos gracias a la mayor conductividad térmica del SiC, lo cual confirma el papel clave que desempeña el sustrato en el autocalentamiento. Se ha observado que la geometría del dispositivo tiene cierta influencia en dichos efectos, destacando que la distribución del calor generado en la zona del canal depende de la distancia entre la puerta y el drenador. Además, se ha demostrado que la temperatura ambiente tiene un considerable impacto en el autocalentamiento, lo que se atribuye principalmente a la dependencia térmica de la conductividad térmica de las capas y sustrato que forman la heterostructura. Por último, se han realizado numerosas medidas en pulsado para estudiar el atrapamiento de carga en HEMTs sobre sustratos de SiC con barreras de AlGaN y de InAlN. Los resultados obtenidos en los transistores con barrera de AlGaN han presentado una disminución de la corriente de drenador y de la transconductancia sin mostrar un cambio en la tensión umbral. Por lo tanto, se puede deducir que la posible localización de las trampas es la región de acceso entre la puerta y el drenador. Por el contrario, la reducción de la corriente de drenador observada en los dispositivos con barrera de InAlN llevaba asociado un cambio significativo en la tensión umbral, lo que implica la existencia de trampas situadas en la zona debajo de la puerta. Además, el significativo aumento del valor de la resistencia-ON y la degradación de la transconductancia revelan la presencia de trampas en la zona de acceso entre la puerta y el drenador. La evaluación de los efectos del atrapamiento de carga en dispositivos con diferentes geometrías ha demostrado que dichos efectos son menos notables en aquellos transistores con mayor longitud de puerta o mayor distancia entre puerta y drenador. Esta dependencia con la geometría se puede explicar considerando que la longitud y densidad de trampas de la puerta virtual son independientes de las dimensiones del dispositivo. Finalmente se puede deducir que para conseguir el diseño óptimo durante la fase de diseño no sólo hay que tener en cuenta la aplicación final sino también la influencia que tiene la geometría en los diferentes aspectos estudiados (funcionamiento a alta temperatura, autocalentamiento, y atrapamiento de carga). ABSTRACT GaN-based high electron mobility transistors have been under extensive research due to the excellent electrical properties of GaN and its related alloys (high carrier concentration, high mobility, and high critical electric field). Although these devices have been recently included in commercial applications, some performance and reliability issues need to be addressed for their expansion in the market. Some of these relevant aspects have been studied during this thesis; for instance, the fabrication of enhancement mode HEMTs, the device performance at high temperature, the self-heating and the charge trapping. Enhancement mode HEMTs have become more attractive mainly because their use leads to a significant reduction of the power consumption during the stand-by state. Moreover, they enable the fabrication of simpler power amplifier circuits and high-power switches because they allow the elimination of negativepolarity voltage supply, reducing significantly the circuit complexity and system cost. In this thesis, different techniques for the fabrication of these devices have been assessed: wet-etching for achieving the gate-recess in InAl(Ga)N/GaN devices and two different fluorine-based treatments (CF4 plasma and F implantation). Regarding the wet-etching, experiments have been carried out in InAl(Ga)N/GaN grown on different substrates: Si, sapphire, and SiC. The total recess of the barrier was achieved after 3 min of etching in devices grown on Si substrate. This suggests that the etch rate can critically depend on the dislocations present in the structure, since the Si exhibits the highest mismatch to GaN. Concerning the fluorine-based treatments, a post-gate thermal annealing was required to recover the damages caused to the structure during the fluorine-treatments. The study of the threshold voltage as a function of this annealing time has revealed that in the case of the plasma-treated devices it become more negative with the time increase. On the contrary, the threshold voltage of implanted HEMTs showed a positive shift when the annealing time was increased, which is attributed to the deep F implantation profile. Plasma-treated HEMTs have exhibited better DC performance at room temperature than the implanted devices. Their study at high temperature has revealed that their performance decreases with temperature. The initial performance measured at room temperature was recovered after the thermal cycle regardless of the fluorine treatment; therefore, the thermal effects were reversible. Thermal issues related to the device performance at different temperature have been addressed. Firstly, AlGaN/GaN HEMTs grown on Si substrate with different cap layers: GaN, in situ SiN, or in situ SiN/GaN, have been assessed from 25 K to 550 K. In situ SiN cap layer has been demonstrated to improve the device performance since HEMTs with this cap layer have exhibited the highest drain current and transconductance values, the lowest on-resistance, as well as the best off-state characteristics. Moreover, the evaluation of thermal stress impact on the device performance has confirmed the robustness of devices with in situ cap. Secondly, the high temperature performance of InAlN/GaN HEMTs with different layouts and geometries have been assessed. The devices under study have exhibited an almost linear reduction of the main DC parameters operating in a temperature range from room temperature to 225°C. This was mainly due to the thermal dependence of the electron mobility, and secondly to the drift velocity decrease with temperature. Moreover, HEMTs with large gate length values have exhibited a great reduction of the device performance. This was attributed to the greater decrease of the drift velocity for low electric fields. Similarly, the increase of the gate-to-drain distance led to a greater reduction of drain current and transconductance values. Therefore, this thermal performance degradation has been found to be dependent on both the gate length and the gate-to-drain distance. It was observed that the very high power density in the active region of these transistors leads to Joule self-heating, resulting in an increase of the device temperature, which can degrade the device performance and reliability. A simple electrical method have been developed during this work to determine the channel temperature. Furthermore, the application of this technique together with the performance of electro-thermal simulations have enabled the evaluation of different aspects related to the self-heating. For instance, the influence of the substrate have been confirmed by the study of devices grown on Si, SiC, and Sapphire. HEMTs grown on SiC substrate have been confirmed to exhibit the lowest self-heating effects thanks to its highest thermal conductivity. In addition to this, the distribution of the generated heat in the channel has been demonstrated to be dependent on the gate-to-drain distance. Besides the substrate and the geometry of the device, the ambient temperature has also been found to be relevant for the self-heating effects, mainly due to the temperature-dependent thermal conductivity of the layers and the substrate. Trapping effects have been evaluated by means of pulsed measurements in AlGaN and InAIN barrier devices. AlGaN barrier HEMTs have exhibited a de crease in drain current and transconductance without measurable threshold voltage change, suggesting the location of the traps in the gate-to-drain access region. On the contrary, InAIN barrier devices have showed a drain current associated with a positive shift of threshold voltage, which indicated that the traps were possibly located under the gate region. Moreover, a significant increase of the ON-resistance as well as a transconductance reduction were observed, revealing the presence of traps on the gate-drain access region. On the other hand, the assessment of devices with different geometries have demonstrated that the trapping effects are more noticeable in devices with either short gate length or the gate-to-drain distance. This can be attributed to the fact that the length and the trap density of the virtual gate are independent on the device geometry. Finally, it can be deduced that besides the final application requirements, the influence of the device geometry on the performance at high temperature, on the self-heating, as well as on the trapping effects need to be taken into account during the device design stage to achieve the optimal layout.