Guide to intermediate band solar cell research

The intermediate band solar cell (IBSC) is a solar cell that, in order to increase its efficiency over that of single gap solar cells, takes advantage of the absorption of below-bandgap energy photons by means of an intermediate band (IB) located in the semiconductor bandgap. For this process to improve the solar cell performance, the belowbandgap photon absorption has to be effective and the IB cannot limit the open-circuit voltage of the cell. In this paper we provide a guide to the new researcher interested in the idea in order he can quickly become familiar with the concept and updated with the most relevant experimental results.

Conductivity variations of multi-walled carbon nanotubes oriented in liquid crystal cells

The control of carbon nanotubes conductivity is generating interest in several fields since it may be relevant for a number of applications. The self-organizing properties of liquid crystals may be used to impose alignment on dispersed carbon nanotubes,thus control-ling their conductivity and its anisotropy. This leads to a number of possible applications in photonic and electronic devices such as electrically controlled carbon nanotube switch- es and crossboards. In this work, cells of liquid crystals doped with multi-walled nanotubes have been prepared in different configurations. Their conductivity variations upon switching have been investigated. It turns out that conductivity evolution depends on the initial configuration (either homogeneous, homeotropic or in-plane switching), the cell thickness and the switching record. The control of these manufacturing paramenters allows the modulation of the electrical behavior of carbon nanotubes.

Evaluation of the PV cell operation temperature in the process of fast switching to open-circuit mode

A procedure for measuring the overheating temperature (ΔT ) of a p-n junction area in the structure of photovoltaic (PV) cells converting laser or solar radiations relative to the ambient temperature has been proposed for the conditions of connecting to an electric load. The basis of the procedure is the measurement of the open-circuit voltage (VO C ) during the initial time period after the fast disconnection of the external resistive load. The simultaneous temperature control on an external heated part of a PV module gives the means for determining the value of VO C at ambient temperature. Comparing it with that measured after switching OFF the load makes the calculation of ΔT possible. Calibration data on the VO C = f(T ) dependences for single-junction AlGaAs/GaAs and triple-junction InGaP/GaAs/Ge PV cells are presented. The temperature dynamics in the PV cells has been determined under flash illumination and during fast commutation of the load. Temperature measurements were taken in two cases: converting continuous laser power by single-junction cells and converting solar power by triple-junction cells operating in the concentrator modules.

Two-photon photocurrent and voltage up-conversion in a quantum dot intermediate band solar cell

It has been proposed that the use of self-assembled quantum dot (QD) arrays can break the Shockley-Queisser efficiency limit by extending the absorption of solar cells into the low-energy photon range while preserving their output voltage. This would be possible if the infrared photons are absorbed in the two sub-bandgap QD transitions simultaneously and the energy of two photons is added up to produce one single electron-hole pair, as described by the intermediate band model. Here, we present an InAs/Al 0.25Ga 0.75As QD solar cell that exhibits such electrical up-conversion of low-energy photons. When the device is monochromatically illuminated with 1.32 eV photons, open-circuit voltages as high as 1.58 V are measured (for a total gap of 1.8 eV). Moreover, the photocurrent produced by illumination with photons exciting the valence band to intermediate band (VB-IB) and the intermediate band to conduction band (IB-CB) transitions can be both spectrally resolved. The first corresponds to the QD inter-band transition and is observable for photons of energy mayor que 1 eV, and the later corresponds to the QD intra-band transition and peaks around 0.5 eV. The voltage up-conversion process reported here for the first time is the key to the use of the low-energy end of the solar spectrum to increase the conversion efficiency, and not only the photocurrent, of single-junction photovoltaic devices. In spite of the low absorption threshold measured in our devices - 0.25 eV - we report open-circuit voltages at room temperature as high as 1.12 V under concentrated broadband illumination.

Nanotechnology for more efficient photovoltaics: the quantum dot intermediate band solar cell

The intermediate band solar cell [1] has been proposed as a concept able to substantially enhance the efficiency limit of an ordinary single junction solar cell. If a band permitted for electrons is inserted within the forbidden band of a semiconductor then a novel path for photo generation is open: electron hole pairs may be formed by the successive absorption of two sub band gap photons using the intermediate band (IB) as a stepping stone. While the increase of the photovoltaic (PV) current is not a big achievement —it suffices to reduce the band gap— the achievement of this extra current at high voltage is the key of the IB concept. In ordinary cells the voltage is limited by the band gap so that reducing it would also reduce the band gap. In the intermediate band solar cell the high voltage is produced when the IB is permitted to have a Quasi Fermi Level (QFL) different from those of the Conduction Band (CB) and the Valence Band (VB). For it the cell must be properly isolated from the external contacts, which is achieved by putting the IB material between two n- and p-type ordinary semiconductors [2]. Efficiency thermodynamic limit of 63% is obtained for the IB solar cell1 vs. the 40% obtained [3] for ordinary single junction solar cells. Detailed information about the IB solar cells can be found elsewhere [4].

On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors

La temperatura es una preocupación que juega un papel protagonista en el diseño de circuitos integrados modernos. El importante aumento de las densidades de potencia que conllevan las últimas generaciones tecnológicas ha producido la aparición de gradientes térmicos y puntos calientes durante el funcionamiento normal de los chips. La temperatura tiene un impacto negativo en varios parámetros del circuito integrado como el retardo de las puertas, los gastos de disipación de calor, la fiabilidad, el consumo de energía, etc. Con el fin de luchar contra estos efectos nocivos, la técnicas de gestión dinámica de la temperatura (DTM) adaptan el comportamiento del chip en función en la información que proporciona un sistema de monitorización que mide en tiempo de ejecución la información térmica de la superficie del dado. El campo de la monitorización de la temperatura en el chip ha llamado la atención de la comunidad científica en los últimos años y es el objeto de estudio de esta tesis. Esta tesis aborda la temática de control de la temperatura en el chip desde diferentes perspectivas y niveles, ofreciendo soluciones a algunos de los temas más importantes. Los niveles físico y circuital se cubren con el diseño y la caracterización de dos nuevos sensores de temperatura especialmente diseñados para los propósitos de las técnicas DTM. El primer sensor está basado en un mecanismo que obtiene un pulso de anchura variable dependiente de la relación de las corrientes de fuga con la temperatura. De manera resumida, se carga un nodo del circuito y posteriormente se deja flotando de tal manera que se descarga a través de las corrientes de fugas de un transistor; el tiempo de descarga del nodo es la anchura del pulso. Dado que la anchura del pulso muestra una dependencia exponencial con la temperatura, la conversión a una palabra digital se realiza por medio de un contador logarítmico que realiza tanto la conversión tiempo a digital como la linealización de la salida. La estructura resultante de esta combinación de elementos se implementa en una tecnología de 0,35 _m. El sensor ocupa un área muy reducida, 10.250 nm2, y consume muy poca energía, 1.05-65.5nW a 5 muestras/s, estas cifras superaron todos los trabajos previos en el momento en que se publicó por primera vez y en el momento de la publicación de esta tesis, superan a todas las implementaciones anteriores fabricadas en el mismo nodo tecnológico. En cuanto a la precisión, el sensor ofrece una buena linealidad, incluso sin calibrar; se obtiene un error 3_ de 1,97oC, adecuado para tratar con las aplicaciones de DTM. Como se ha explicado, el sensor es completamente compatible con los procesos de fabricación CMOS, este hecho, junto con sus valores reducidos de área y consumo, lo hacen especialmente adecuado para la integración en un sistema de monitorización de DTM con un conjunto de monitores empotrados distribuidos a través del chip. Las crecientes incertidumbres de proceso asociadas a los últimos nodos tecnológicos comprometen las características de linealidad de nuestra primera propuesta de sensor. Con el objetivo de superar estos problemas, proponemos una nueva técnica para obtener la temperatura. La nueva técnica también está basada en las dependencias térmicas de las corrientes de fuga que se utilizan para descargar un nodo flotante. La novedad es que ahora la medida viene dada por el cociente de dos medidas diferentes, en una de las cuales se altera una característica del transistor de descarga |la tensión de puerta. Este cociente resulta ser muy robusto frente a variaciones de proceso y, además, la linealidad obtenida cumple ampliamente los requisitos impuestos por las políticas DTM |error 3_ de 1,17oC considerando variaciones del proceso y calibrando en dos puntos. La implementación de la parte sensora de esta nueva técnica implica varias consideraciones de diseño, tales como la generación de una referencia de tensión independiente de variaciones de proceso, que se analizan en profundidad en la tesis. Para la conversión tiempo-a-digital, se emplea la misma estructura de digitalización que en el primer sensor. Para la implementación física de la parte de digitalización, se ha construido una biblioteca de células estándar completamente nueva orientada a la reducción de área y consumo. El sensor resultante de la unión de todos los bloques se caracteriza por una energía por muestra ultra baja (48-640 pJ) y un área diminuta de 0,0016 mm2, esta cifra mejora todos los trabajos previos. Para probar esta afirmación, se realiza una comparación exhaustiva con más de 40 propuestas de sensores en la literatura científica. Subiendo el nivel de abstracción al sistema, la tercera contribución se centra en el modelado de un sistema de monitorización que consiste de un conjunto de sensores distribuidos por la superficie del chip. Todos los trabajos anteriores de la literatura tienen como objetivo maximizar la precisión del sistema con el mínimo número de monitores. Como novedad, en nuestra propuesta se introducen nuevos parámetros de calidad aparte del número de sensores, también se considera el consumo de energía, la frecuencia de muestreo, los costes de interconexión y la posibilidad de elegir diferentes tipos de monitores. El modelo se introduce en un algoritmo de recocido simulado que recibe la información térmica de un sistema, sus propiedades físicas, limitaciones de área, potencia e interconexión y una colección de tipos de monitor; el algoritmo proporciona el tipo seleccionado de monitor, el número de monitores, su posición y la velocidad de muestreo _optima. Para probar la validez del algoritmo, se presentan varios casos de estudio para el procesador Alpha 21364 considerando distintas restricciones. En comparación con otros trabajos previos en la literatura, el modelo que aquí se presenta es el más completo. Finalmente, la última contribución se dirige al nivel de red, partiendo de un conjunto de monitores de temperatura de posiciones conocidas, nos concentramos en resolver el problema de la conexión de los sensores de una forma eficiente en área y consumo. Nuestra primera propuesta en este campo es la introducción de un nuevo nivel en la jerarquía de interconexión, el nivel de trillado (o threshing en inglés), entre los monitores y los buses tradicionales de periféricos. En este nuevo nivel se aplica selectividad de datos para reducir la cantidad de información que se envía al controlador central. La idea detrás de este nuevo nivel es que en este tipo de redes la mayoría de los datos es inútil, porque desde el punto de vista del controlador sólo una pequeña cantidad de datos |normalmente sólo los valores extremos| es de interés. Para cubrir el nuevo nivel, proponemos una red de monitorización mono-conexión que se basa en un esquema de señalización en el dominio de tiempo. Este esquema reduce significativamente tanto la actividad de conmutación sobre la conexión como el consumo de energía de la red. Otra ventaja de este esquema es que los datos de los monitores llegan directamente ordenados al controlador. Si este tipo de señalización se aplica a sensores que realizan conversión tiempo-a-digital, se puede obtener compartición de recursos de digitalización tanto en tiempo como en espacio, lo que supone un importante ahorro de área y consumo. Finalmente, se presentan dos prototipos de sistemas de monitorización completos que de manera significativa superan la características de trabajos anteriores en términos de área y, especialmente, consumo de energía. Abstract Temperature is a first class design concern in modern integrated circuits. The important increase in power densities associated to recent technology evolutions has lead to the apparition of thermal gradients and hot spots during run time operation. Temperature impacts several circuit parameters such as speed, cooling budgets, reliability, power consumption, etc. In order to fight against these negative effects, dynamic thermal management (DTM) techniques adapt the behavior of the chip relying on the information of a monitoring system that provides run-time thermal information of the die surface. The field of on-chip temperature monitoring has drawn the attention of the scientific community in the recent years and is the object of study of this thesis. This thesis approaches the matter of on-chip temperature monitoring from different perspectives and levels, providing solutions to some of the most important issues. The physical and circuital levels are covered with the design and characterization of two novel temperature sensors specially tailored for DTM purposes. The first sensor is based upon a mechanism that obtains a pulse with a varying width based on the variations of the leakage currents on the temperature. In a nutshell, a circuit node is charged and subsequently left floating so that it discharges away through the subthreshold currents of a transistor; the time the node takes to discharge is the width of the pulse. Since the width of the pulse displays an exponential dependence on the temperature, the conversion into a digital word is realized by means of a logarithmic counter that performs both the timeto- digital conversion and the linearization of the output. The structure resulting from this combination of elements is implemented in a 0.35_m technology and is characterized by very reduced area, 10250 nm2, and power consumption, 1.05-65.5 nW at 5 samples/s, these figures outperformed all previous works by the time it was first published and still, by the time of the publication of this thesis, they outnumber all previous implementations in the same technology node. Concerning the accuracy, the sensor exhibits good linearity, even without calibration it displays a 3_ error of 1.97oC, appropriate to deal with DTM applications. As explained, the sensor is completely compatible with standard CMOS processes, this fact, along with its tiny area and power overhead, makes it specially suitable for the integration in a DTM monitoring system with a collection of on-chip monitors distributed across the chip. The exacerbated process fluctuations carried along with recent technology nodes jeop-ardize the linearity characteristics of the first sensor. In order to overcome these problems, a new temperature inferring technique is proposed. In this case, we also rely on the thermal dependencies of leakage currents that are used to discharge a floating node, but now, the result comes from the ratio of two different measures, in one of which we alter a characteristic of the discharging transistor |the gate voltage. This ratio proves to be very robust against process variations and displays a more than suficient linearity on the temperature |1.17oC 3_ error considering process variations and performing two-point calibration. The implementation of the sensing part based on this new technique implies several issues, such as the generation of process variations independent voltage reference, that are analyzed in depth in the thesis. In order to perform the time-to-digital conversion, we employ the same digitization structure the former sensor used. A completely new standard cell library targeting low area and power overhead is built from scratch to implement the digitization part. Putting all the pieces together, we achieve a complete sensor system that is characterized by ultra low energy per conversion of 48-640pJ and area of 0.0016mm2, this figure outperforms all previous works. To prove this statement, we perform a thorough comparison with over 40 works from the scientific literature. Moving up to the system level, the third contribution is centered on the modeling of a monitoring system consisting of set of thermal sensors distributed across the chip. All previous works from the literature target maximizing the accuracy of the system with the minimum number of monitors. In contrast, we introduce new metrics of quality apart form just the number of sensors; we consider the power consumption, the sampling frequency, the possibility to consider different types of monitors and the interconnection costs. The model is introduced in a simulated annealing algorithm that receives the thermal information of a system, its physical properties, area, power and interconnection constraints and a collection of monitor types; the algorithm yields the selected type of monitor, the number of monitors, their position and the optimum sampling rate. We test the algorithm with the Alpha 21364 processor under several constraint configurations to prove its validity. When compared to other previous works in the literature, the modeling presented here is the most complete. Finally, the last contribution targets the networking level, given an allocated set of temperature monitors, we focused on solving the problem of connecting them in an efficient way from the area and power perspectives. Our first proposal in this area is the introduction of a new interconnection hierarchy level, the threshing level, in between the monitors and the traditional peripheral buses that applies data selectivity to reduce the amount of information that is sent to the central controller. The idea behind this new level is that in this kind of networks most data are useless because from the controller viewpoint just a small amount of data |normally extreme values| is of interest. To cover the new interconnection level, we propose a single-wire monitoring network based on a time-domain signaling scheme that significantly reduces both the switching activity over the wire and the power consumption of the network. This scheme codes the information in the time domain and allows a straightforward obtention of an ordered list of values from the maximum to the minimum. If the scheme is applied to monitors that employ TDC, digitization resource sharing is achieved, producing an important saving in area and power consumption. Two prototypes of complete monitoring systems are presented, they significantly overcome previous works in terms of area and, specially, power consumption.

Envelope amplifier based on switching capacitors for high efficiency RF amplifiers

Modern transmitters usually have to amplify and transmit signals with simultaneous envelope and phase modulation. Due to this property of the transmitted signal, linear power amplifiers (class A, B, or AB) are usually used as a solution for the power amplifier stage. These amplifiers have high linearity, but suffer from low efficiency when the transmitted signal has high peak-to-average power ratio. The Kahn envelope elimination and restoration technique is used to enhance the efficiency of RF transmitters, by combining highly efficient, nonlinear RF amplifier (class E) with a highly efficient envelope amplifier in order to obtain a linear and highly efficient RF amplifier. This paper presents a solution for the envelope amplifier based on a multilevel converter in series with a linear regulator. The multilevel converter is implemented by employing voltage dividers based on switching capacitors. The implemented envelope amplifier can reproduce any signal with a maximum spectral component of 2 MHz and give instantaneous maximum power of 50 W. The efficiency measurements show that when the signals with low average value are transmitted, the implemented prototypes have up to 20% higher efficiency than linear regulators used as a conventional solution.

Three-level cell topology for a multilevel power supply to achieve High

This paper presents an envelope amplifier solution for envelope elimination and restoration (EER), that consists of a series combination of a switch-mode power supply (SMPS), based on three-level voltage cells and a linear regulator. This cell topology offers several advantages over a previously presented envelope amplifier based on a different multilevel topology (two-level voltage cells). The topology of the multilevel converter affects to the whole design of the envelope amplifier and a comparison between both design alternatives regarding the size, complexity and the efficiency of the solution is done. Both envelope amplifier solutions have a bandwidth of 2 MHz with an instantaneous maximum power of 50 W. It is also analyzed the linearity of the three-level cell solution, with critical importance in the EER technique implementation. Additionally, considerations to optimize the design of the envelope amplifier and experimental comparison between both cell topologies are included.

Voltage recovery in intermediate band solar cells

The intermediate band solar cell (IBSC) is based on a novel photovoltaic concept and has a limiting efficiency of 63.2%, which compares favorably with the 40.7% efficiency of a conventional, single junction solar cell. It is characterized by a material hosting a collection of energy levels within its bandgap, allowing the cell to exploit photons with sub-bandgap energies in a two-step absorption process, thus improving the utilization of the solar spectrum. However, these intermediate levels are often regarded as an inherent source of supplementary recombination, although this harmful effect can in theory be counteracted by the use of concentrated light. We present here a novel, low-temperature characterization technique using concentrated light that reveals how the initially enhanced recombination in the IBSC is reduced so that its open-circuit voltage is completely recovered and reaches that of a conventional solar cell.

Understanding experimental characterization of intermediate band solar cell

An intermediate band solar cell is a novel photovoltaic device with the potential to exceed the efficiency of single gap solar cells. In the last few years, several prototypes of these cells, based on different technologies, have been reported. Since these devices do not yet perform ideally, it is sometimes difficult to determine to what extent they operate as actual intermediate band solar cells. In this article we provide the essential guidelines to interpret conventional experimental results (current-voltage plots, quantum efficiency, etc.) associated with their characterization. A correct interpretation of these results is essential in order not to mislead the research efforts directed towards the improvement of the efficiency of these devices.

Comparison of V2IC control with voltage mode and current mode controls for high frequency (MHz) and very fast response applications

High switching frequencies (several MHz) allow the integration of low power DC/DC converters. Although, in theory, a high switching frequency would make possible to implement a conventional Voltage Mode control (VMC) or Peak Current Mode control (PCMC) with very high bandwidth, in practice, parasitic effects and robustness limits the applicability of these control techniques. This paper compares VMC and CMC techniques with the V2IC control. This control is based on two loops. The fast internal loop has information of the output capacitor current and the error voltage, providing fast dynamic response under load and voltage reference steps, while the slow external voltage loop provides accurate steady state regulation. This paper shows the fast dynamic response of the V2IC control under load and output voltage reference steps and its robustness operating with additional output capacitors added by the customer.

Sistema de instrumentação e controle para células a combustível

Este trabajo presenta un estudio sobre el funcionamiento y aplicaciones de las células de combustible de membrana tipo PEM, o de intercambio de protones, alimentadas con hidrógeno puro y oxigeno obtenido de aire comprimido. Una vez evaluado el proceso de dichas células y las variables que intervienen en el mismo, como presión, humedad y temperatura, se presenta una variedad de métodos para la instrumentación de tales variables así como métodos y sistemas para la estabilidad y control de las mismas, en torno a los valores óptimos para una mayor eficacia en el proceso. Tomando como variable principal a controlar la temperatura del proceso, y exponiendo los valores concretos en torno a 80 grados centígrados entre los que debe situarse, es realizado un modelo del proceso de calentamiento y evolución de la temperatura en función de la potencia del calentador resistivo en el dominio de la frecuencia compleja, y a su vez implementado un sistema de medición mediante sensores termopar de tipo K de respuesta casi lineal. La señal medida por los sensores es amplificada de manera diferencial mediante amplificadores de instrumentación INA2126, y es desarrollado un algoritmo de corrección de error de unión fría (error producido por la inclusión de nuevos metales del conector en el efecto termopar). Son incluidos los datos de test referentes al sistema de medición de temperatura , incluyendo las desviaciones o error respecto a los valores ideales de medida. Para la adquisición de datos y implementación de algoritmos de control, es utilizado un PC con el software Labview de National Instruments, que permite una programación intuitiva, versátil y visual, y poder realizar interfaces de usuario gráficas simples. La conexión entre el hardware de instrumentación y control de la célula y el PC se realiza mediante un interface de adquisición de datos USB NI 6800 que cuenta con un amplio número de salidas y entradas analógicas. Una vez digitalizadas las muestras de la señal medida, y corregido el error de unión fría anteriormente apuntado, es implementado en dicho software un controlador de tipo PID ( proporcional-integral-derivativo) , que se presenta como uno de los métodos más adecuados por su simplicidad de programación y su eficacia para el control de este tipo de variables. Para la evaluación del comportamiento del sistema son expuestas simulaciones mediante el software Matlab y Simulink determinando por tanto las mejores estrategias para desarrollar el control PID, así como los posibles resultados del proceso. En cuanto al sistema de calentamiento de los fluidos, es empleado un elemento resistor calentador, cuya potencia es controlada mediante un circuito electrónico compuesto por un detector de cruce por cero de la onda AC de alimentación y un sistema formado por un elemento TRIAC y su circuito de accionamiento. De manera análoga se expone el sistema de instrumentación para la presión de los gases en el circuito, variable que oscila en valores próximos a 3 atmosferas, para ello es empleado un sensor de presión con salida en corriente mediante bucle 4-20 mA, y un convertidor simple corriente a tensión para la entrada al sistema de adquisición de datos. Consecuentemente se presenta el esquema y componentes necesarios para la canalización, calentamiento y humidificación de los gases empleados en el proceso así como la situación de los sensores y actuadores. Por último el trabajo expone la relación de algoritmos desarrollados y un apéndice con información relativa al software Labview. ABTRACT This document presents a study about the operation and applications of PEM fuel cells (Proton exchange membrane fuel cells), fed with pure hydrogen and oxygen obtained from compressed air. Having evaluated the process of these cells and the variables involved on it, such as pressure, humidity and temperature, there is a variety of methods for implementing their control and to set up them around optimal values for greater efficiency in the process. Taking as primary process variable the temperature, and exposing its correct values around 80 degrees centigrade, between which must be placed, is carried out a model of the heating process and the temperature evolution related with the resistive heater power on the complex frequency domain, and is implemented a measuring system with thermocouple sensor type K performing a almost linear response. The differential signal measured by the sensor is amplified through INA2126 instrumentation amplifiers, and is developed a cold junction error correction algorithm (error produced by the inclusion of additional metals of connectors on the thermocouple effect). Data from the test concerning the temperature measurement system are included , including deviations or error regarding the ideal values of measurement. For data acquisition and implementation of control algorithms, is used a PC with LabVIEW software from National Instruments, which makes programming intuitive, versatile, visual, and useful to perform simple user interfaces. The connection between the instrumentation and control hardware of the cell and the PC interface is via a USB data acquisition NI 6800 that has a large number of analog inputs and outputs. Once stored the samples of the measured signal, and correct the error noted above junction, is implemented a software controller PID (proportional-integral-derivative), which is presented as one of the best methods for their programming simplicity and effectiveness for the control of such variables. To evaluate the performance of the system are presented simulations using Matlab and Simulink software thereby determining the best strategies to develop PID control, and possible outcomes of the process. As fluid heating system, is employed a heater resistor element whose power is controlled by an electronic circuit comprising a zero crossing detector of the AC power wave and a system consisting of a Triac and its drive circuit. As made with temperature variable it is developed an instrumentation system for gas pressure in the circuit, variable ranging in values around 3 atmospheres, it is employed a pressure sensor with a current output via 4-20 mA loop, and a single current to voltage converter to adequate the input to the data acquisition system. Consequently is developed the scheme and components needed for circulation, heating and humidification of the gases used in the process as well as the location of sensors and actuators. Finally the document presents the list of algorithms and an appendix with information about Labview software.

A puzzling solar cell structure: an exercise to get insight on intermediate band solar cells

We introduce one trivial but puzzling solar cell structure. It consists of a high bandgap pn junction (top cell) grown on a substrate of lower bandgap. Let us assume, for example, that the bandgap of the top cell is 1.85 eV (Al 0.3Ga 0.7As) and the bandgap of the substrate is 1.42 eV (GaAs). Is the open-circuit of the top cell limited to 1.42 V or to 1.85 V? If the answer is ldquo1.85 Vrdquo we could then make the mind experiment in which we illuminate the cell with 1.5 eV photons (notice these photons would only be absorbed in the substrate). If we admit that these photons can generate photocurrent, then because we have also admitted that the voltage is limited to 1.85 V, it might be possible that the electron-hole pairs generated by these photons were extracted at 1.6 V for example. However, if we do so, the principles of thermodynamics could be violated because we would be extracting more energy from the photon than the energy it initially had. How can we then solve this puzzle?

Wide bandwidth envelope trackers with reduced switching frequency for RF power amplifier

El requerimiento de proveer alta frecuencia de datos en los modernos sistema de comunicación inalámbricos resulta en complejas señales moduladas de radio-frequencia (RF) con un gran ancho de banda y alto ratio pico-promedio (PAPR). Para garantizar la linealidad del comportamiento, los amplificadores lineales de potencia comunes funcionan típicamente entre 4 y 10 dB de back-o_ desde la máxima potencia de salida, ocasionando una baja eficiencia del sistema. La eliminación y restauración de la evolvente (EER) y el seguimiento de la evolvente (ET) son dos prometedoras técnicas para resolver el problema de la eficiencia. Tanto en EER como en ET, es complicado diseñar un amplificador de potencia que sea eficiente para señales de RF de alto ancho de banda y alto PAPR. Una propuesta común para los amplificadores de potencia es incluir un convertidor de potencia de muy alta eficiencia operando a frecuencias más altas que el ancho de banda de la señal RF. En este caso, la potencia perdida del convertidor ocasionado por la alta frecuencia desaconseja su práctica cuando el ancho de banda es muy alto. La solución a este problema es el enfoque de esta disertación que presenta dos arquitecturas de amplificador evolvente: convertidor híbrido-serie con una técnica de evolvente lenta y un convertidor multinivel basado en un convertidor reductor multifase con control de tiempo mínimo. En la primera arquitectura, una topología híbrida está compuesta de una convertidor reductor conmutado y un regulador lineal en serie que trabajan juntos para ajustar la tensión de salida para seguir a la evolvente con precisión. Un algoritmo de generación de una evolvente lenta crea una forma de onda con una pendiente limitada que es menor que la pendiente máxima de la evolvente original. La salida del convertidor reductor sigue esa forma de onda en vez de la evolvente original usando una menor frecuencia de conmutación, porque la forma de onda no sólo tiene una pendiente reducida sino también un menor ancho de banda. De esta forma, el regulador lineal se usa para filtrar la forma de onda tiene una pérdida de potencia adicional. Dependiendo de cuánto se puede reducir la pendiente de la evolvente para producir la forma de onda, existe un trade-off entre la pérdida de potencia del convertidor reductor relacionada con la frecuencia de conmutación y el regulador lineal. El punto óptimo referido a la menor pérdida de potencia total del amplificador de evolvente es capaz de identificarse con la ayuda de modelo preciso de pérdidas que es una combinación de modelos comportamentales y analíticos de pérdidas. Además, se analiza el efecto en la respuesta del filtro de salida del convertidor reductor. Un filtro de dampeo paralelo extra es necesario para eliminar la oscilación resonante del filtro de salida porque el convertidor reductor opera en lazo abierto. La segunda arquitectura es un amplificador de evolvente de seguimiento de tensión multinivel. Al contrario que los convertidores que usan multi-fuentes, un convertidor reductor multifase se emplea para generar la tensión multinivel. En régimen permanente, el convertidor reductor opera en puntos del ciclo de trabajo con cancelación completa del rizado. El número de niveles de tensión es igual al número de fases de acuerdo a las características del entrelazamiento del convertidor reductor. En la transición, un control de tiempo mínimo (MTC) para convertidores multifase es novedosamente propuesto y desarrollado para cambiar la tensión de salida del convertidor reductor entre diferentes niveles. A diferencia de controles convencionales de tiempo mínimo para convertidores multifase con inductancia equivalente, el propuesto MTC considera el rizado de corriente por cada fase basado en un desfase fijo que resulta en diferentes esquemas de control entre las fases. La ventaja de este control es que todas las corrientes vuelven a su fase en régimen permanente después de la transición para que la siguiente transición pueda empezar muy pronto, lo que es muy favorable para la aplicación de seguimiento de tensión multinivel. Además, el control es independiente de la carga y no es afectado por corrientes de fase desbalanceadas. Al igual que en la primera arquitectura, hay una etapa lineal con la misma función, conectada en serie con el convertidor reductor multifase. Dado que tanto el régimen permanente como el estado de transición del convertidor no están fuertemente relacionados con la frecuencia de conmutación, la frecuencia de conmutación puede ser reducida para el alto ancho de banda de la evolvente, la cual es la principal consideración de esta arquitectura. La optimización de la segunda arquitectura para más alto anchos de banda de la evolvente es presentada incluyendo el diseño del filtro de salida, la frecuencia de conmutación y el número de fases. El área de diseño del filtro está restringido por la transición rápida y el mínimo pulso del hardware. La rápida transición necesita un filtro pequeño pero la limitación del pulso mínimo del hardware lleva el diseño en el sentido contrario. La frecuencia de conmutación del convertidor afecta principalmente a la limitación del mínimo pulso y a las pérdidas de potencia. Con una menor frecuencia de conmutación, el ancho de pulso en la transición es más pequeño. El número de fases relativo a la aplicación específica puede ser optimizado en términos de la eficiencia global. Otro aspecto de la optimización es mejorar la estrategia de control. La transición permite seguir algunas partes de la evolvente que son más rápidas de lo que el hardware puede soportar al precio de complejidad. El nuevo método de sincronización de la transición incrementa la frecuencia de la transición, permitiendo que la tensión multinivel esté más cerca de la evolvente. Ambas estrategias permiten que el convertidor pueda seguir una evolvente con un ancho de banda más alto que la limitación de la etapa de potencia. El modelo de pérdidas del amplificador de evolvente se ha detallado y validado mediante medidas. El mecanismo de pérdidas de potencia del convertidor reductor tiene que incluir las transiciones en tiempo real, lo cual es diferente del clásico modelos de pérdidas de un convertidor reductor síncrono. Este modelo estima la eficiencia del sistema y juega un papel muy importante en el proceso de optimización. Finalmente, la segunda arquitectura del amplificador de evolvente se integra con el amplificador de clase F. La medida del sistema EER prueba el ahorro de energía con el amplificador de evolvente propuesto sin perjudicar la linealidad del sistema. ABSTRACT The requirement of delivering high data rates in modern wireless communication systems results in complex modulated RF signals with wide bandwidth and high peak-to-average ratio (PAPR). In order to guarantee the linearity performance, the conventional linear power amplifiers typically work at 4 to 10 dB back-off from the maximum output power, leading to low system efficiency. The envelope elimination and restoration (EER) and envelope tracking (ET) are two promising techniques to overcome the efficiency problem. In both EER and ET, it is challenging to design efficient envelope amplifier for wide bandwidth and high PAPR RF signals. An usual approach for envelope amplifier includes a high-efficiency switching power converter operating at a frequency higher than the RF signal's bandwidth. In this case, the power loss of converter caused by high switching operation becomes unbearable for system efficiency when signal bandwidth is very wide. The solution of this problem is the focus of this dissertation that presents two architectures of envelope amplifier: a hybrid series converter with slow-envelope technique and a multilevel converter based on a multiphase buck converter with the minimum time control. In the first architecture, a hybrid topology is composed of a switched buck converter and a linear regulator in series that work together to adjust the output voltage to track the envelope with accuracy. A slow envelope generation algorithm yields a waveform with limited slew rate that is lower than the maximum slew rate of the original envelope. The buck converter's output follows this waveform instead of the original envelope using lower switching frequency, because the waveform has not only reduced slew rate but also reduced bandwidth. In this way, the linear regulator used to filter the waveform has additional power loss. Depending on how much reduction of the slew rate of envelope in order to obtain that waveform, there is a trade-off between the power loss of buck converter related to the switching frequency and the power loss of linear regulator. The optimal point referring to the lowest total power loss of this envelope amplifier is identified with the help of a precise power loss model that is a combination of behavioral and analytic loss model. In addition, the output filter's effect on the response is analyzed. An extra parallel damping filter is needed to eliminate the resonant oscillation of output filter L and C, because the buck converter operates in open loop. The second architecture is a multilevel voltage tracking envelope amplifier. Unlike the converters using multi-sources, a multiphase buck converter is employed to generate the multilevel voltage. In the steady state, the buck converter operates at complete ripple cancellation points of duty cycle. The number of the voltage levels is equal to the number of phases according the characteristics of interleaved buck converter. In the transition, a minimum time control (MTC) for multiphase converter is originally proposed and developed for changing the output voltage of buck converter between different levels. As opposed to conventional minimum time control for multiphase converter with equivalent inductance, the proposed MTC considers the current ripple of each phase based on the fixed phase shift resulting in different control schemes among the phases. The advantage of this control is that all the phase current return to the steady state after the transition so that the next transition can be triggered very soon, which is very favorable for the application of multilevel voltage tracking. Besides, the control is independent on the load condition and not affected by the unbalance of phase current. Like the first architecture, there is also a linear stage with the same function, connected in series with the multiphase buck converter. Since both steady state and transition state of the converter are not strongly related to the switching frequency, it can be reduced for wide bandwidth envelope which is the main consideration of this architecture. The optimization of the second architecture for wider bandwidth envelope is presented including the output filter design, switching frequency and the number of phases. The filter design area is restrained by fast transition and the minimum pulse of hardware. The fast transition needs small filter but the minimum pulse of hardware limitation pushes the filter in opposite way. The converter switching frequency mainly affects the minimum pulse limitation and the power loss. With lower switching frequency, the pulse width in the transition is smaller. The number of phases related to specific application can be optimized in terms of overall efficiency. Another aspect of optimization is improving control strategy. Transition shift allows tracking some parts of envelope that are faster than the hardware can support at the price of complexity. The new transition synchronization method increases the frequency of transition, allowing the multilevel voltage to be closer to the envelope. Both control strategies push the converter to track wider bandwidth envelope than the limitation of power stage. The power loss model of envelope amplifier is detailed and validated by measurements. The power loss mechanism of buck converter has to include the transitions in real time operation, which is different from classical power loss model of synchronous buck converter. This model estimates the system efficiency and play a very important role in optimization process. Finally, the second envelope amplifier architecture is integrated with a Class F amplifier. EER system measurement proves the power saving with the proposed envelope amplifier without disrupting the linearity performance.

High-Power High-Efficiency Laser Power Transmission at 100m Using Optimized Multi-Cell GaAs Converter

A high-power high-efficiency laser power transmission system at 100m based on an optimized multi-cell GaAs converter capable of supplying 9.7W of electricity is demonstrated. An I-V testing system integrated with a data acquisition circuit and an analysis software is designed to measure the efficiency and the I-V characteristics of the laser power converter (LPC). The dependencies of the converter’s efficiency with respect to wavelength, laser intensity and temperature are analyzed. A diode laser with 793nm of wavelength and 24W of power is used to test the LPC and the software. The maximum efficiency of the LPC is 48.4% at an input laser power of 8W at room temperature. When the input laser power is 24W (laser intensity of 60000W/m2), the efficiency is 40.4% and the output voltage is 4 V. The overall efficiency from electricity to electricity is 11.6%.