A framework for the analysis and optimization of delay in multiview video coding schemes

Esta tesis presenta un novedoso marco de referencia para el análisis y optimización del retardo de codificación y descodificación para vídeo multivista. El objetivo de este marco de referencia es proporcionar una metodología sistemática para el análisis del retardo en codificadores y descodificadores multivista y herramientas útiles en el diseño de codificadores/descodificadores para aplicaciones con requisitos de bajo retardo. El marco de referencia propuesto caracteriza primero los elementos que tienen influencia en el comportamiento del retardo: i) la estructura de predicción multivista, ii) el modelo hardware del codificador/descodificador y iii) los tiempos de proceso de cuadro. En segundo lugar, proporciona algoritmos para el cálculo del retardo de codificación/ descodificación de cualquier estructura arbitraria de predicción multivista. El núcleo de este marco de referencia consiste en una metodología para el análisis del retardo de codificación/descodificación multivista que es independiente de la arquitectura hardware del codificador/descodificador, completada con un conjunto de modelos que particularizan este análisis del retardo con las características de la arquitectura hardware del codificador/descodificador. Entre estos modelos, aquellos basados en teoría de grafos adquieren especial relevancia debido a su capacidad de desacoplar la influencia de los diferentes elementos en el comportamiento del retardo en el codificador/ descodificador, mediante una abstracción de su capacidad de proceso. Para revelar las posibles aplicaciones de este marco de referencia, esta tesis presenta algunos ejemplos de su utilización en problemas de diseño que afectan a codificadores y descodificadores multivista. Este escenario de aplicación cubre los siguientes casos: estrategias para el diseño de estructuras de predicción que tengan en consideración requisitos de retardo además del comportamiento tasa-distorsión; diseño del número de procesadores y análisis de los requisitos de velocidad de proceso en codificadores/ descodificadores multivista dado un retardo objetivo; y el análisis comparativo del comportamiento del retardo en codificadores multivista con diferentes capacidades de proceso e implementaciones hardware. ABSTRACT This thesis presents a novel framework for the analysis and optimization of the encoding and decoding delay for multiview video. The objective of this framework is to provide a systematic methodology for the analysis of the delay in multiview encoders and decoders and useful tools in the design of multiview encoders/decoders for applications with low delay requirements. The proposed framework characterizes firstly the elements that have an influence in the delay performance: i) the multiview prediction structure ii) the hardware model of the encoder/decoder and iii) frame processing times. Secondly, it provides algorithms for the computation of the encoding/decoding delay of any arbitrary multiview prediction structure. The core of this framework consists in a methodology for the analysis of the multiview encoding/decoding delay that is independent of the hardware architecture of the encoder/decoder, which is completed with a set of models that particularize this delay analysis with the characteristics of the hardware architecture of the encoder/decoder. Among these models, the ones based in graph theory acquire special relevance due to their capacity to detach the influence of the different elements in the delay performance of the encoder/decoder, by means of an abstraction of its processing capacity. To reveal possible applications of this framework, this thesis presents some examples of its utilization in design problems that affect multiview encoders and decoders. This application scenario covers the following cases: strategies for the design of prediction structures that take into consideration delay requirements in addition to the rate-distortion performance; design of number of processors and analysis of processor speed requirements in multiview encoders/decoders given a target delay; and comparative analysis of the encoding delay performance of multiview encoders with different processing capabilities and hardware implementations.

Depth perceptual video coding for free viewpoint video based on H.264/AVC

A novel scheme for depth sequences compression, based on a perceptual coding algorithm, is proposed. A depth sequence describes the object position in the 3D scene, and is used, in Free Viewpoint Video, for the generation of synthetic video sequences. In perceptual video coding the human visual system characteristics are exploited to improve the compression efficiency. As depth sequences are never shown, the perceptual video coding, assessed over them, is not effective. The proposed algorithm is based on a novel perceptual rate distortion optimization process, assessed over the perceptual distortion of the rendered views generated through the encoded depth sequences. The experimental results show the effectiveness of the proposed method, able to obtain a very considerable improvement of the rendered view perceptual quality.

Estimating Perceived Video Quality from Objective Parameters in Video over IP Services

In Video over IP services, perceived video quality heavily depends on parameters such as video coding and network Quality of Service. This paper proposes a model for the estimation of perceived video quality in video streaming and broadcasting services that combines the aforementioned parameters with other that depend mainly on the information contents of the video sequences. These fitting parameters are derived from the Spatial and Temporal Information contents of the sequences. This model does not require reference to the original video sequence so it can be used for online, real-time monitoring of perceived video quality in Video over IP services. Furthermore, this paper proposes a measurement workbench designed to acquire both training data for model fitting and test data for model validation. Preliminary results show good correlation between measured and predicted values.

Perceived Video Quality Estimation from Spatial and Temporal Information Contents and Network Performance Parameters in IPTV

The paper proposes a model for estimation of perceived video quality in IPTV, taking as input both video coding and network Quality of Service parameters. It includes some fitting parameters that depend mainly on the information contents of the video sequences. A method to derive them from the Spatial and Temporal Information contents of the sequences is proposed. The model may be used for near real-time monitoring of IPTV video quality.

A graph-based approach for latency modeling and optimization in multiview video encoding

We present a novel framework for encoding latency analysis of arbitrary multiview video coding prediction structures. This framework avoids the need to consider an specific encoder architecture for encoding latency analysis by assuming an unlimited processing capacity on the multiview encoder. Under this assumption, only the influence of the prediction structure and the processing times have to be considered, and the encoding latency is solved systematically by means of a graph model. The results obtained with this model are valid for a multiview encoder with sufficient processing capacity and serve as a lower bound otherwise. Furthermore, with the objective of low latency encoder design with low penalty on rate-distortion performance, the graph model allows us to identify the prediction relationships that add higher encoding latency to the encoder. Experimental results for JMVM prediction structures illustrate how low latency prediction structures with a low rate-distortion penalty can be derived in a systematic manner using the new model.

Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs

Systems relying on fixed hardware components with a static level of parallelism can suffer from an underuse of logical resources, since they have to be designed for the worst-case scenario. This problem is especially important in video applications due to the emergence of new flexible standards, like Scalable Video Coding (SVC), which offer several levels of scalability. In this paper, Dynamic and Partial Reconfiguration (DPR) of modern FPGAs is used to achieve run-time variable parallelism, by using scalable architectures where the size can be adapted at run-time. Based on this proposal, a scalable Deblocking Filter core (DF), compliant with the H.264/AVC and SVC standards has been designed. This scalable DF allows run-time addition or removal of computational units working in parallel. Scalability is offered together with a scalable parallelization strategy at the macroblock (MB) level, such that when the size of the architecture changes, MB filtering order is modified accordingly

Methodologies for implement video decoders over multiprocessor platforms

The latest video coding standards developed, like HEVC (High Efficiency Video Coding, approved in January 2013), require for their implementation the use of devices able to support a high computational load. Considering that currently it is not enough the usage of one unique Digital Signal Processor (DSP), multicore devices have appeared recently in the market. However, due to its novelty, the working methodology that allows produce solutions for these configurations is in a very initial state, since currently the most part of the work needs to be performed manually. In consequence, the objective set consists on finding methodologies that ease this process. The study has been focused on extend a methodology, under development, for the generation of solutions for PCs and embedded systems. During this study, the standards RVC (Reconfigurable Video Coding) and HEVC have been employed, as well as DSPs of the Texas Instruments company. In its development, it has been tried to address all the factors that influence both the development and deployment of these new implementations of video decoders, ranging from tools up to aspects of the partitioning of algorithms, without this can cause a drop in application performance. The results of this study are the description of the employed methodology, the characterization of the software migration process and performance measurements for the HEVC standard in an RVC-based implementation. RESUMEN Los estándares de codificación de vídeo desarrollados más recientemente, como HEVC (High Efficiency Video Coding, aprobado en enero de 2013), requieren para su implementación el uso de dispositivos capaces de soportar una elevada carga computacional. Teniendo en cuenta que actualmente no es suficiente con utilizar un único Procesador Digital de Señal (DSP), han aparecido recientemente dispositivos multinúcleo en el mercado. Sin embargo, debido a su novedad, la metodología de trabajo que permite elaborar soluciones para tales configuraciones se encuentra en un estado muy inicial, ya que actualmente la mayor parte del trabajo debe realizarse manualmente. En consecuencia, el objetivo marcado consiste en encontrar metodologías que faciliten este proceso. El estudio se ha centrado en extender una metodología, en desarrollo, para la generación de soluciones para PC y sistemas empotrados. Durante dicho estudio se han empleado los estándares RVC (Reconfigurable Video Coding) y HEVC, así como DSPs de la compañía Texas Instruments. En su desarrollo se ha tratado de atender a todos los factores que influyen tanto en el desarrollo como en la puesta en marcha de estas nuevas implementaciones de descodificadores de vídeo; abarcando desde las herramientas a utilizar hasta aspectos del particionado de los algoritmos, sin que por ello se produzca una reducción en el rendimiento de las aplicaciones. Los resultados de este estudio son una descripción de la metodología empleada, la caracterización del proceso de migración de software, y medidas de rendimiento para el estándar HEVC en una implementación basada en RVC.

Adaptive protection scheme for MVC-encoded stereoscopic video streaming in IP-based networks

We present an adaptive unequal error protection (UEP) strategy built on the 1-D interleaved parity Application Layer Forward Error Correction (AL-FEC) code for protecting the transmission of stereoscopic 3D video content encoded with Multiview Video Coding (MVC) through IP-based networks. Our scheme targets the minimization of quality degradation produced by packet losses during video transmission in time-sensitive application scenarios. To that end, based on a novel packet-level distortion model, it selects in real time the most suitable packets within each Group of Pictures (GOP) to be protected and the most convenient FEC technique parameters, i.e., the size of the FEC generator matrix. In order to make these decisions, it considers the relevance of the packet, the behavior of the channel, and the available bitrate for protection purposes. Simulation results validate both the distortion model introduced to estimate the importance of packets and the optimization of the FEC technique parameter values.

Reconfigurable video code (RVC) : aplicación para automatizar la asignación de procesos RUC a los núcleos de un sistema multiprocesador

El esquema actual que existe en el ámbito de la normalización y el diseño de nuevos estándares de codificación de vídeo se está convirtiendo en una tarea difícil de satisfacer la evolución y dinamismo de la comunidad de codificación de vídeo. El problema estaba centrado principalmente en poder explotar todas las características y similitudes entre los diferentes códecs y estándares de codificación. Esto ha obligado a tener que rediseñar algunas partes comunes a varios estándares de codificación. Este problema originó la aparición de una nueva iniciativa de normalización dentro del comité ISO/IEC MPEG, llamado Reconfigurable Video Coding (RVC). Su principal idea era desarrollar un estándar de codificación de vídeo que actualizase e incrementase progresivamente una biblioteca de los componentes, aportando flexibilidad y la capacidad de tener un código reconfigurable mediante el uso de un nuevo lenguaje orientado a flujo de Actores/datos denominado CAL. Este lenguaje se usa para la especificación de la biblioteca estándar y para la creación de instancias del modelo del decodificador. Más tarde, se desarrolló un nuevo estándar de codificación de vídeo denominado High Efficiency Video Coding (HEVC), que actualmente se encuentra en continuo proceso de actualización y desarrollo, que mejorase la eficiencia y compresión de la codificación de vídeo. Obviamente se ha desarrollado una visión de HEVC empleando la metodología de RVC. En este PFC, se emplean diferentes implementaciones de estándares empleando RVC. Por ejemplo mediante los decodificadores Mpeg 4 Part 2 SP y Mpeg 4 Part 10 CBP y PHP así como del nuevo estándar de codificación HEVC, resaltando las características y utilidad de cada uno de ellos. En RVC los algoritmos se describen mediante una clase de actores que intercambian flujos de datos (tokens) para realizar diferentes acciones. El objetivo de este proyecto es desarrollar un programa que, partiendo de los decodificadores anteriormente mencionados, una serie de secuencia de vídeo en diferentes formatos de compresión y una distribución estándar de los actores (para cada uno de los decodificadores), sea capaz de generar diferentes distribuciones de los actores del decodificador sobre uno o varios procesadores del sistema sobre el que se ejecuta, para conseguir la mayor eficiencia en la codificación del vídeo. La finalidad del programa desarrollado en este proyecto es la de facilitar la realización de las distribuciones de los actores sobre los núcleos del sistema, y obtener las mejores configuraciones posibles de una manera automática y eficiente. ABSTRACT. The current scheme that exists in the field of standardization and the design of new video coding standards is becoming a difficult task to meet the evolving and dynamic community of video encoding. The problem was centered mainly in order to exploit all the features and similarities between different codecs and encoding standards. This has forced redesigning some parts common to several coding standards. This problem led to the emergence of a new initiative for standardization within the ISO / IEC MPEG committee, called Reconfigurable Video Coding (RVC). His main idea was to develop a video coding standard and gradually incrementase to update a library of components, providing flexibility and the ability to have a reconfigurable code using a new flow -oriented language Actors / data called CAL. This language is used for the specification of the standard library and to the instantiation model decoder. Later, a new video coding standard called High Efficiency Video Coding (HEVC), which currently is in continuous process of updating and development, which would improve the compression efficiency and video coding is developed. Obviously has developed a vision of using the methodology HEVC RVC. In this PFC, different implementations using RVC standard are used. For example, using decoders MPEG 4 Part 2 SP and MPEG 4 Part 10 CBP and PHP and the new coding standard HEVC, highlighting the features and usefulness of each. In RVC, the algorithms are described by a class of actors that exchange streams of data (tokens) to perform different actions. The objective of this project is to develop a program that, based on the aforementioned decoders, a series of video stream in different compression formats and a standard distribution of actors (for each of the decoders), is capable of generating different distributions decoder actors on one or more processors of the system on which it runs, to achieve greater efficiency in video coding. The purpose of the program developed in this project is to facilitate the realization of the distributions of the actors on the cores of the system, and get the best possible settings automatically and efficiently.

Systematic analysis of the decoding delay in multiview video

We present a framework for the analysis of the decoding delay in multiview video coding (MVC). We show that in real-time applications, an accurate estimation of the decoding delay is essential to achieve a minimum communication latency. As opposed to single-view codecs, the complexity of the multiview prediction structure and the parallel decoding of several views requires a systematic analysis of this decoding delay, which we solve using graph theory and a model of the decoder hardware architecture. Our framework assumes a decoder implementation in general purpose multi-core processors with multi-threading capabilities. For this hardware model, we show that frame processing times depend on the computational load of the decoder and we provide an iterative algorithm to compute jointly frame processing times and decoding delay. Finally, we show that decoding delay analysis can be applied to design decoders with the objective of minimizing the communication latency of the MVC system.

The DLMT. An alternative to the DCT

In the last recent years, with the popularity of image compression techniques, many architectures have been proposed. Those have been generally based on the Forward and Inverse Discrete Cosine Transform (FDCT, IDCT). Alternatively, compression schemes based on discrete “wavelets” transform (DWT), used, both, in JPEG2000 coding standard and in the next H264-SVC (Scalable Video Coding), do not need to divide the image into non-overlapping blocks or macroblocks. This paper discusses the DLMT (Discrete Lopez-Moreno Transform). It proposes a new scheme intermediate between the DCT and the DWT (Discrete Wavelet Transform). The DLMT is computationally very similar to the DCT and uses quasi-sinusoidal functions, so the emergence of artifact blocks and their effects have a relative low importance. The use of quasi-sinusoidal functions has allowed achieving a multiresolution control quite close to that obtained by a DWT, but without increasing the computational complexity of the transformation. The DLMT can also be applied over a whole image, but this does not involve increasing computational complexity. Simulation results in MATLAB show that the proposed DLMT has significant performance benefits and improvements comparing with the DCT

Estudio de calidad de codificación utilizando los perfiles 10 Bits del estándar H.264

Desde los inicios de la codificación de vídeo digital hasta hoy, tanto la señal de video sin comprimir de entrada al codificador como la señal de salida descomprimida del decodificador, independientemente de su resolución, uso de submuestreo en los planos de diferencia de color, etc. han tenido siempre la característica común de utilizar 8 bits para representar cada una de las muestras. De la misma manera, los estándares de codificación de vídeo imponen trabajar internamente con estos 8 bits de precisión interna al realizar operaciones con las muestras cuando aún no se han transformado al dominio de la frecuencia. Sin embargo, el estándar H.264, en gran auge hoy en día, permite en algunos de sus perfiles orientados al mundo profesional codificar vídeo con más de 8 bits por muestra. Cuando se utilizan estos perfiles, las operaciones efectuadas sobre las muestras todavía sin transformar se realizan con la misma precisión que el número de bits del vídeo de entrada al codificador. Este aumento de precisión interna tiene el potencial de permitir unas predicciones más precisas, reduciendo el residuo a codificar y aumentando la eficiencia de codificación para una tasa binaria dada. El objetivo de este Proyecto Fin de Carrera es estudiar, utilizando las medidas de calidad visual objetiva PSNR (Peak Signal to Noise Ratio, relación señal ruido de pico) y SSIM (Structural Similarity, similaridad estructural), el efecto sobre la eficiencia de codificación y el rendimiento al trabajar con una cadena de codificación/descodificación H.264 de 10 bits en comparación con una cadena tradicional de 8 bits. Para ello se utiliza el codificador de código abierto x264, capaz de codificar video de 8 y 10 bits por muestra utilizando los perfiles High, High 10, High 4:2:2 y High 4:4:4 Predictive del estándar H.264. Debido a la ausencia de herramientas adecuadas para calcular las medidas PSNR y SSIM de vídeo con más de 8 bits por muestra y un tipo de submuestreo de planos de diferencia de color distinto al 4:2:0, como parte de este proyecto se desarrolla también una aplicación de análisis en lenguaje de programación C capaz de calcular dichas medidas a partir de dos archivos de vídeo sin comprimir en formato YUV o Y4M. ABSTRACT Since the beginning of digital video compression, the uncompressed video source used as input stream to the encoder and the uncompressed decoded output stream have both used 8 bits for representing each sample, independent of resolution, chroma subsampling scheme used, etc. In the same way, video coding standards force encoders to work internally with 8 bits of internal precision when working with samples before being transformed to the frequency domain. However, the H.264 standard allows coding video with more than 8 bits per sample in some of its professionally oriented profiles. When using these profiles, all work on samples still in the spatial domain is done with the same precision the input video has. This increase in internal precision has the potential of allowing more precise predictions, reducing the residual to be encoded, and thus increasing coding efficiency for a given bitrate. The goal of this Project is to study, using PSNR (Peak Signal to Noise Ratio) and SSIM (Structural Similarity) objective video quality metrics, the effects on coding efficiency and performance caused by using an H.264 10 bit coding/decoding chain compared to a traditional 8 bit chain. In order to achieve this goal the open source x264 encoder is used, which allows encoding video with 8 and 10 bits per sample using the H.264 High, High 10, High 4:2:2 and High 4:4:4 Predictive profiles. Given that no proper tools exist for computing PSNR and SSIM values of video with more than 8 bits per sample and chroma subsampling schemes other than 4:2:0, an analysis application written in the C programming language is developed as part of this Project. This application is able to compute both metrics from two uncompressed video files in the YUV or Y4M format.

Integración MPlayer-OpenSVC en el procesador multinúcleo OMAP3530

La constante evolución de dispositivos portátiles multimedia que se ha producido en la última década ha provocado que hoy en día se disponga de una amplia variedad de dispositivos con capacidad para reproducir contenidos multimedia. En consecuencia, la reproducción de esos contenidos en dichos terminales lleva asociada disponer de procesadores que soporten una alta carga computacional, ya que las tareas de descodificación y presentación de video así lo requieren. Sin embargo, un procesador potente trabajando a elevadas frecuencias provoca un elevado consumo de la batería, y dado que se pretende trabajar con dispositivos portátiles, la vida útil de la batería se convierte en un asunto de especial importancia. La problemática que se plantea se ha convertido en una de las principales líneas de investigación del Grupo de Investigación GDEM (Grupo de Diseño Electrónico y Microelectrónico). En esta línea de trabajo, se persigue cómo optimizar el consumo de energía en terminales portables desde el punto de vista de la reducción de la calidad de experiencia del usuario a cambio de una mayor autonomía del terminal. Por tanto, para lograr esa reducción de la calidad de experiencia mencionada, se requiere un estándar de codificación de vídeo que así lo permita. El Grupo de Investigación GDEM cuenta con experiencia en el estándar de vídeo escalable H.264/SVC, el cual permite degradar la calidad de experiencia en función de las necesidades/características del dispositivo. Más concretamente, un video escalable contiene embebidas distintas versiones del video original que pueden ser descodificadas en diferentes resoluciones, tasas de cuadro y calidades (escalabilidades espacial, temporal y de calidad respectivamente), permitiendo una adaptación rápida y muy flexible. Seleccionado el estándar H.264/SVC para las tareas de vídeo, se propone trabajar con Mplayer, un reproductor de vídeos de código abierto (open source), al cual se le ha integrado un descodificador para vídeo escalable denominado OpenSVC. Por último, como dispositivo portable se trabajará con la plataforma de desarrollo BeagleBoard, un sistema embebido basado en el procesador OMAP3530 que permite modificar la frecuencia de reloj y la tensión de alimentación dinámicamente reduciendo de este modo el consumo del terminal. Este procesador a su vez contiene integrados un procesador de propósito general (ARM Cortex-A8) y un procesador digital de señal (DSP TMS320C64+TM). Debido a la alta carga computacional de la descodificación de vídeos escalables y la escasa optimización del ARM para procesamiento de datos, se propone llevar a cabo la ejecución de Mplayer en el ARM y encargar la tarea de descodificación al DSP, con la finalidad de reducir el consumo y por tanto aumentar la vida útil del sistema embebido sobre el cual se ejecutará la aplicación desarrollada. Una vez realizada esa integración, se llevará a cabo una caracterización del descodificador alojado en el DSP a través de una serie de medidas de rendimiento y se compararán los resultados con los obtenidos en el proceso de descodificación realizado únicamente en el ARM. ABSTRACT During the last years, the multimedia portable terminals have gradually evolved causing that nowadays a several range of devices with the ability of playing multimedia contents are easily available for everyone. Consequently, those multimedia terminals must have high-performance processors to play those contents because the coding and decoding tasks demand high computational load. However, a powerful processor performing to high frequencies implies higher battery consumption, and this issue has become one of the most important problems in the development cycle of a portable terminal. The power/energy consumption optimization on multimedia terminals has become in one the most significant work lines in the Electronic and Microelectronic Research Group of the Universidad Politécnica de Madrid. In particular, the group is researching how to reduce the user‟s Quality of Experience (QoE) quality in exchange for increased battery life. In order to reduce the Quality of Experience (QoE), a standard video coding that allows this operation is required. The H.264/SVC allows reducing the QoE according to the needs/characteristics of the terminal. Specifically, a scalable video contains different versions of original video embedded in an only one video stream, and each one of them can be decoded in different resolutions, frame rates and qualities (spatial, temporal and quality scalabilities respectively). Once the standard video coding is selected, a multimedia player with support for scalable video is needed. Mplayer has been proposed as a multimedia player, whose characteristics (open-source, enormous flexibility and scalable video decoder called OpenSVC) are the most suitable for the aims of this Master Thesis. Lastly, the embedded system BeagleBoard, based on the multi-core processor OMAP3530, will be the development platform used in this project. The multimedia terminal architecture is based on a commercial chip having a General Purpose Processor (GPP – ARM Cortex A8) and a Digital Signal Processor (DSP, TMS320C64+™). Moreover, the processor OMAP3530 has the ability to modify the operating frequency and the supply voltage in a dynamic way in order to reduce the power consumption of the embedded system. So, the main goal of this Master Thesis is the integration of the multimedia player, MPlayer, executed at the GPP, and scalable video decoder, OpenSVC, executed at the DSP in order to distribute the computational load associated with the scalable video decoding task and to reduce the power consumption of the terminal. Once the integration is accomplished, the performance of the OpenSVC decoder executed at the DSP will be measured using different combinations of scalability values. The obtained results will be compared with the scalable video decoding performed at the GPP in order to show the low optimization of this kind of architecture for decoding tasks in contrast to DSP architecture.

Exploration of RVC applications using an ARM multicore processor = Exploración de aplicaciones RVC empleando un procesador ARM multinúcleo

Single core capabilities have reached their maximum clock speed; new multicore architectures provide an alternative way to tackle this issue instead. The design of decoding applications running on top of these multicore platforms and their optimization to exploit all system computational power is crucial to obtain best results. Since the development at the integration level of printed circuit boards are increasingly difficult to optimize due to physical constraints and the inherent increase in power consumption, development of multiprocessor architectures is becoming the new Holy Grail. In this sense, it is crucial to develop applications that can run on the new multi-core architectures and find out distributions to maximize the potential use of the system. Today most of commercial electronic devices, available in the market, are composed of embedded systems. These devices incorporate recently multi-core processors. Task management onto multiple core/processors is not a trivial issue, and a good task/actor scheduling can yield to significant improvements in terms of efficiency gains and also processor power consumption. Scheduling of data flows between the actors that implement the applications aims to harness multi-core architectures to more types of applications, with an explicit expression of parallelism into the application. On the other hand, the recent development of the MPEG Reconfigurable Video Coding (RVC) standard allows the reconfiguration of the video decoders. RVC is a flexible standard compatible with MPEG developed codecs, making it the ideal tool to integrate into the new multimedia terminals to decode video sequences. With the new versions of the Open RVC-CAL Compiler (Orcc), a static mapping of the actors that implement the functionality of the application can be done once the application executable has been generated. This static mapping must be done for each of the different cores available on the working platform. It has been chosen an embedded system with a processor with two ARMv7 cores. This platform allows us to obtain the desired tests, get as much improvement results from the execution on a single core, and contrast both with a PC-based multiprocessor system. Las posibilidades ofrecidas por el aumento de la velocidad de la frecuencia de reloj de sistemas de un solo procesador están siendo agotadas. Las nuevas arquitecturas multiprocesador proporcionan una vía de desarrollo alternativa en este sentido. El diseño y optimización de aplicaciones de descodificación de video que se ejecuten sobre las nuevas arquitecturas permiten un mejor aprovechamiento y favorecen la obtención de mayores rendimientos. Hoy en día muchos de los dispositivos comerciales que se están lanzando al mercado están integrados por sistemas embebidos, que recientemente están basados en arquitecturas multinúcleo. El manejo de las tareas de ejecución sobre este tipo de arquitecturas no es una tarea trivial, y una buena planificación de los actores que implementan las funcionalidades puede proporcionar importantes mejoras en términos de eficiencia en el uso de la capacidad de los procesadores y, por ende, del consumo de energía. Por otro lado, el reciente desarrollo del estándar de Codificación de Video Reconfigurable (RVC), permite la reconfiguración de los descodificadores de video. RVC es un estándar flexible y compatible con anteriores codecs desarrollados por MPEG. Esto hace de RVC el estándar ideal para ser incorporado en los nuevos terminales multimedia que se están comercializando. Con el desarrollo de las nuevas versiones del compilador específico para el desarrollo de lenguaje RVC-CAL (Orcc), en el que se basa MPEG RVC, el mapeo estático, para entornos basados en multiprocesador, de los actores que integran un descodificador es posible. Se ha elegido un sistema embebido con un procesador con dos núcleos ARMv7. Esta plataforma nos permitirá llevar a cabo las pruebas de verificación y contraste de los conceptos estudiados en este trabajo, en el sentido del desarrollo de descodificadores de video basados en MPEG RVC y del estudio de la planificación y mapeo estático de los mismos.

The DLMT hardware implementation. A comparative study with the DCT and the DWT

In the last recent years, with the popularity of image compression techniques, many architectures have been proposed. Those have been generally based on the Forward and Inverse Discrete Cosine Transform (FDCT, IDCT). Alternatively, compression schemes based on discrete "wavelets" transform (DWT), used, both, in JPEG2000 coding standard and in H264-SVC (Scalable Video Coding) standard, do not need to divide the image into non-overlapping blocks or macroblocks. This paper discusses the DLMT (Discrete Lopez-Moreno Transform) hardware implementation. It proposes a new scheme intermediate between the DCT and the DWT, comparing results of the most relevant proposed architectures for benchmarking. The DLMT can also be applied over a whole image, but this does not involve increasing computational complexity. FPGA implementation results show that the proposed DLMT has significant performance benefits and improvements comparing with the DCT and the DWT and consequently it is very suitable for implementation on WSN (Wireless Sensor Network) applications.