Urban microclimate and thermal comfort modelling: strategies for urban renovation

The urban microclimate plays an important role in building energy consumption and thermal comfort in outdoor spaces. Nowadays, cities need to increase energy efficiency, reduce pollutant emissions and mitigate the evident lack of sustainability. In light of this, attention has focused on the bioclimatic concepts use in the urban development. However, the speculative unsustainability of the growth model highlights the need to redirect the construction sector towards urban renovation using a bioclimatic approach. The public space plays a key role in improving the quality of today’s cities, especially in terms of providing places for citizens to meet and socialize in adequate thermal conditions. Thermal comfort affects perception of the environment, so microclimate conditions can be decisive for the success or failure of outdoor urban spaces and the activities held in them. For these reasons, the main focus of this work is on the definition of bioclimatic strategies for existing urban spaces, based on morpho-typological components, urban microclimate conditions and comfort requirements for all kinds of citizens. Two case studies were selected in Madrid, in a social housing neighbourhood constructed in the 1970s based on Rational Architecture style. Several renovation scenarios were performed using a computer simulation process based in ENVI-met and diverse microclimate conditions were compared. In addition, thermal comfort evaluation was carried out using the Universal Thermal Climate Index (UTCI) in order to investigate the relationship between microclimate conditions and thermal comfort perception. This paper introduces the microclimate computer simulation process as a valuable support for decision-making for neighbourhood renovation projects in order to provide new and better solutions according to the thermal quality of public spaces and reducing energy consumption by creating and selecting better microclimate areas.

On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors

La temperatura es una preocupación que juega un papel protagonista en el diseño de circuitos integrados modernos. El importante aumento de las densidades de potencia que conllevan las últimas generaciones tecnológicas ha producido la aparición de gradientes térmicos y puntos calientes durante el funcionamiento normal de los chips. La temperatura tiene un impacto negativo en varios parámetros del circuito integrado como el retardo de las puertas, los gastos de disipación de calor, la fiabilidad, el consumo de energía, etc. Con el fin de luchar contra estos efectos nocivos, la técnicas de gestión dinámica de la temperatura (DTM) adaptan el comportamiento del chip en función en la información que proporciona un sistema de monitorización que mide en tiempo de ejecución la información térmica de la superficie del dado. El campo de la monitorización de la temperatura en el chip ha llamado la atención de la comunidad científica en los últimos años y es el objeto de estudio de esta tesis. Esta tesis aborda la temática de control de la temperatura en el chip desde diferentes perspectivas y niveles, ofreciendo soluciones a algunos de los temas más importantes. Los niveles físico y circuital se cubren con el diseño y la caracterización de dos nuevos sensores de temperatura especialmente diseñados para los propósitos de las técnicas DTM. El primer sensor está basado en un mecanismo que obtiene un pulso de anchura variable dependiente de la relación de las corrientes de fuga con la temperatura. De manera resumida, se carga un nodo del circuito y posteriormente se deja flotando de tal manera que se descarga a través de las corrientes de fugas de un transistor; el tiempo de descarga del nodo es la anchura del pulso. Dado que la anchura del pulso muestra una dependencia exponencial con la temperatura, la conversión a una palabra digital se realiza por medio de un contador logarítmico que realiza tanto la conversión tiempo a digital como la linealización de la salida. La estructura resultante de esta combinación de elementos se implementa en una tecnología de 0,35 _m. El sensor ocupa un área muy reducida, 10.250 nm2, y consume muy poca energía, 1.05-65.5nW a 5 muestras/s, estas cifras superaron todos los trabajos previos en el momento en que se publicó por primera vez y en el momento de la publicación de esta tesis, superan a todas las implementaciones anteriores fabricadas en el mismo nodo tecnológico. En cuanto a la precisión, el sensor ofrece una buena linealidad, incluso sin calibrar; se obtiene un error 3_ de 1,97oC, adecuado para tratar con las aplicaciones de DTM. Como se ha explicado, el sensor es completamente compatible con los procesos de fabricación CMOS, este hecho, junto con sus valores reducidos de área y consumo, lo hacen especialmente adecuado para la integración en un sistema de monitorización de DTM con un conjunto de monitores empotrados distribuidos a través del chip. Las crecientes incertidumbres de proceso asociadas a los últimos nodos tecnológicos comprometen las características de linealidad de nuestra primera propuesta de sensor. Con el objetivo de superar estos problemas, proponemos una nueva técnica para obtener la temperatura. La nueva técnica también está basada en las dependencias térmicas de las corrientes de fuga que se utilizan para descargar un nodo flotante. La novedad es que ahora la medida viene dada por el cociente de dos medidas diferentes, en una de las cuales se altera una característica del transistor de descarga |la tensión de puerta. Este cociente resulta ser muy robusto frente a variaciones de proceso y, además, la linealidad obtenida cumple ampliamente los requisitos impuestos por las políticas DTM |error 3_ de 1,17oC considerando variaciones del proceso y calibrando en dos puntos. La implementación de la parte sensora de esta nueva técnica implica varias consideraciones de diseño, tales como la generación de una referencia de tensión independiente de variaciones de proceso, que se analizan en profundidad en la tesis. Para la conversión tiempo-a-digital, se emplea la misma estructura de digitalización que en el primer sensor. Para la implementación física de la parte de digitalización, se ha construido una biblioteca de células estándar completamente nueva orientada a la reducción de área y consumo. El sensor resultante de la unión de todos los bloques se caracteriza por una energía por muestra ultra baja (48-640 pJ) y un área diminuta de 0,0016 mm2, esta cifra mejora todos los trabajos previos. Para probar esta afirmación, se realiza una comparación exhaustiva con más de 40 propuestas de sensores en la literatura científica. Subiendo el nivel de abstracción al sistema, la tercera contribución se centra en el modelado de un sistema de monitorización que consiste de un conjunto de sensores distribuidos por la superficie del chip. Todos los trabajos anteriores de la literatura tienen como objetivo maximizar la precisión del sistema con el mínimo número de monitores. Como novedad, en nuestra propuesta se introducen nuevos parámetros de calidad aparte del número de sensores, también se considera el consumo de energía, la frecuencia de muestreo, los costes de interconexión y la posibilidad de elegir diferentes tipos de monitores. El modelo se introduce en un algoritmo de recocido simulado que recibe la información térmica de un sistema, sus propiedades físicas, limitaciones de área, potencia e interconexión y una colección de tipos de monitor; el algoritmo proporciona el tipo seleccionado de monitor, el número de monitores, su posición y la velocidad de muestreo _optima. Para probar la validez del algoritmo, se presentan varios casos de estudio para el procesador Alpha 21364 considerando distintas restricciones. En comparación con otros trabajos previos en la literatura, el modelo que aquí se presenta es el más completo. Finalmente, la última contribución se dirige al nivel de red, partiendo de un conjunto de monitores de temperatura de posiciones conocidas, nos concentramos en resolver el problema de la conexión de los sensores de una forma eficiente en área y consumo. Nuestra primera propuesta en este campo es la introducción de un nuevo nivel en la jerarquía de interconexión, el nivel de trillado (o threshing en inglés), entre los monitores y los buses tradicionales de periféricos. En este nuevo nivel se aplica selectividad de datos para reducir la cantidad de información que se envía al controlador central. La idea detrás de este nuevo nivel es que en este tipo de redes la mayoría de los datos es inútil, porque desde el punto de vista del controlador sólo una pequeña cantidad de datos |normalmente sólo los valores extremos| es de interés. Para cubrir el nuevo nivel, proponemos una red de monitorización mono-conexión que se basa en un esquema de señalización en el dominio de tiempo. Este esquema reduce significativamente tanto la actividad de conmutación sobre la conexión como el consumo de energía de la red. Otra ventaja de este esquema es que los datos de los monitores llegan directamente ordenados al controlador. Si este tipo de señalización se aplica a sensores que realizan conversión tiempo-a-digital, se puede obtener compartición de recursos de digitalización tanto en tiempo como en espacio, lo que supone un importante ahorro de área y consumo. Finalmente, se presentan dos prototipos de sistemas de monitorización completos que de manera significativa superan la características de trabajos anteriores en términos de área y, especialmente, consumo de energía. Abstract Temperature is a first class design concern in modern integrated circuits. The important increase in power densities associated to recent technology evolutions has lead to the apparition of thermal gradients and hot spots during run time operation. Temperature impacts several circuit parameters such as speed, cooling budgets, reliability, power consumption, etc. In order to fight against these negative effects, dynamic thermal management (DTM) techniques adapt the behavior of the chip relying on the information of a monitoring system that provides run-time thermal information of the die surface. The field of on-chip temperature monitoring has drawn the attention of the scientific community in the recent years and is the object of study of this thesis. This thesis approaches the matter of on-chip temperature monitoring from different perspectives and levels, providing solutions to some of the most important issues. The physical and circuital levels are covered with the design and characterization of two novel temperature sensors specially tailored for DTM purposes. The first sensor is based upon a mechanism that obtains a pulse with a varying width based on the variations of the leakage currents on the temperature. In a nutshell, a circuit node is charged and subsequently left floating so that it discharges away through the subthreshold currents of a transistor; the time the node takes to discharge is the width of the pulse. Since the width of the pulse displays an exponential dependence on the temperature, the conversion into a digital word is realized by means of a logarithmic counter that performs both the timeto- digital conversion and the linearization of the output. The structure resulting from this combination of elements is implemented in a 0.35_m technology and is characterized by very reduced area, 10250 nm2, and power consumption, 1.05-65.5 nW at 5 samples/s, these figures outperformed all previous works by the time it was first published and still, by the time of the publication of this thesis, they outnumber all previous implementations in the same technology node. Concerning the accuracy, the sensor exhibits good linearity, even without calibration it displays a 3_ error of 1.97oC, appropriate to deal with DTM applications. As explained, the sensor is completely compatible with standard CMOS processes, this fact, along with its tiny area and power overhead, makes it specially suitable for the integration in a DTM monitoring system with a collection of on-chip monitors distributed across the chip. The exacerbated process fluctuations carried along with recent technology nodes jeop-ardize the linearity characteristics of the first sensor. In order to overcome these problems, a new temperature inferring technique is proposed. In this case, we also rely on the thermal dependencies of leakage currents that are used to discharge a floating node, but now, the result comes from the ratio of two different measures, in one of which we alter a characteristic of the discharging transistor |the gate voltage. This ratio proves to be very robust against process variations and displays a more than suficient linearity on the temperature |1.17oC 3_ error considering process variations and performing two-point calibration. The implementation of the sensing part based on this new technique implies several issues, such as the generation of process variations independent voltage reference, that are analyzed in depth in the thesis. In order to perform the time-to-digital conversion, we employ the same digitization structure the former sensor used. A completely new standard cell library targeting low area and power overhead is built from scratch to implement the digitization part. Putting all the pieces together, we achieve a complete sensor system that is characterized by ultra low energy per conversion of 48-640pJ and area of 0.0016mm2, this figure outperforms all previous works. To prove this statement, we perform a thorough comparison with over 40 works from the scientific literature. Moving up to the system level, the third contribution is centered on the modeling of a monitoring system consisting of set of thermal sensors distributed across the chip. All previous works from the literature target maximizing the accuracy of the system with the minimum number of monitors. In contrast, we introduce new metrics of quality apart form just the number of sensors; we consider the power consumption, the sampling frequency, the possibility to consider different types of monitors and the interconnection costs. The model is introduced in a simulated annealing algorithm that receives the thermal information of a system, its physical properties, area, power and interconnection constraints and a collection of monitor types; the algorithm yields the selected type of monitor, the number of monitors, their position and the optimum sampling rate. We test the algorithm with the Alpha 21364 processor under several constraint configurations to prove its validity. When compared to other previous works in the literature, the modeling presented here is the most complete. Finally, the last contribution targets the networking level, given an allocated set of temperature monitors, we focused on solving the problem of connecting them in an efficient way from the area and power perspectives. Our first proposal in this area is the introduction of a new interconnection hierarchy level, the threshing level, in between the monitors and the traditional peripheral buses that applies data selectivity to reduce the amount of information that is sent to the central controller. The idea behind this new level is that in this kind of networks most data are useless because from the controller viewpoint just a small amount of data |normally extreme values| is of interest. To cover the new interconnection level, we propose a single-wire monitoring network based on a time-domain signaling scheme that significantly reduces both the switching activity over the wire and the power consumption of the network. This scheme codes the information in the time domain and allows a straightforward obtention of an ordered list of values from the maximum to the minimum. If the scheme is applied to monitors that employ TDC, digitization resource sharing is achieved, producing an important saving in area and power consumption. Two prototypes of complete monitoring systems are presented, they significantly overcome previous works in terms of area and, specially, power consumption.

Influence of the application of Jasmonic Acid and Benzoic Acid on Watermelon fruit quality.

In watermelon crops in Southeastern Spain, important thermal differences appear during the first stages of plant development that can affect them. This work shows the effect of applying jasmonic acid and benzoic acid (JA+BA), inductors of systemic acquired resistance (SAR) and induced systemic resistance (ISR), respectively, on fruit quality parameters from a crop in a greenhouse in Southeastern Spain, where crops face a remarkable abiotic stress. We assessed two treatments of JA+BA, T1 (500+500 ppm), T2 (2000+2000 ppm) and a control test using an experimental design of randomized blocks with four replications. The results obtained for the parameters assessed (ºBrix, flesh firmness, rind thickness, polar and equatorial diameter) did not show statistically significant differences. The results showed that there was no metabolic cost in the plants when applying the assessed treatments of JA+BA.

New laser-based approaches to improve the passivation and rear contact quality in high effiency crystalline silicon solar cells

Laser processing has been the tool of choice last years to develop improved concepts in contact formation for high efficiency crystalline silicon (c-Si) solar cells. New concepts based on standard laser fired contacts (LFC) or advanced laser doping (LD) techniques are optimal solutions for both the front and back contacts of a number of structures with growing interest in the c-Si PV industry. Nowadays, substantial efforts are underway to optimize these processes in order to be applied industrially in high efficiency concepts. However a critical issue in these devices is that, most of them, demand a very low thermal input during the fabrication sequence and a minimal damage of the structure during the laser irradiation process. Keeping these two objectives in mind, in this work we discuss the possibility of using laser-based processes to contact the rear side of silicon heterojunction (SHJ) solar cells in an approach fully compatible with the low temperature processing associated to these devices. First we discuss the possibility of using standard LFC techniques in the fabrication of SHJ cells on p-type substrates, studying in detail the effect of the laser wavelength on the contact quality. Secondly, we present an alternative strategy bearing in mind that a real challenge in the rear contact formation is to reduce the damage induced by the laser irradiation. This new approach is based on local laser doping techniques previously developed by our groups, to contact the rear side of p-type c-Si solar cells by means of laser processing before rear metallization of dielectric stacks containing Al2O3. In this work we demonstrate the possibility of using this new approach in SHJ cells with a distinct advantage over other standard LFC techniques.

Deposition reactors for solar grade silicon: a comparative thermal analysis of a Siemens reactor and a fluidized bed reactor

Polysilicon production costs contribute approximately to 25-33% of the overall cost of the solar panels and a similar fraction of the total energy invested in their fabrication. Understanding the energy losses and the behaviour of process temperature is an essential requirement as one moves forward to design and build large scale polysilicon manufacturing plants. In this paper we present thermal models for two processes for poly production, viz., the Siemens process using trichlorosilane (TCS) as precursor and the fluid bed process using silane (monosilane, MS).We validate the models with some experimental measurements on prototype laboratory reactors relating the temperature profiles to product quality. A model sensitivity analysis is also performed, and the efects of some key parameters such as reactor wall emissivity, gas distributor temperature, etc., on temperature distribution and product quality are examined. The information presented in this paper is useful for further understanding of the strengths and weaknesses of both deposition technologies, and will help in optimal temperature profiling of these systems aiming at lowering production costs without compromising the solar cell quality.

Muro cortina modular con marco de baja transmitancia térmica integrado en el vidrio aislante a través de adhesivos estructurales = Unitised curtain wall with low thermal transmittance frame integrated within the insulating glass unit through structural adhesives

Los muros cortina modulares están constituidos por paneles prefabricados que se fijan al edificio a través de anclajes a lo largo del borde del forjado. El proceso de prefabricación garantiza buena calidad y control de los acabados y el proceso de instalación es rápido y no requiere andamiaje. Por estas razones su uso está muy extendido en torres. Sin embargo, el diseño de los marcos de aluminio podría ser más eficiente si se aprovechara la rigidez de los vidrios para reducir la profundidad estructural de los montantes. Asimismo, se podrían reducir los puentes térmicos en las juntas si se sustituyeran los marcos por materiales de menor conductividad térmica que el aluminio. Esta investigación persigue desarrollar un muro cortina alternativo que reduzca la profundidad estructural, reduzca la transmisión térmica en las juntas y permita un acabado enrasado al interior, sin que sobresalgan los montantes. La idea consiste en conectar un marco de material compuesto de fibra de vidrio a lo largo del borde del vidrio aislante a través de adhesivos estructurales para así movilizar una acción estructural compuesta entre los dos vidrios y lograr una baja transmitancia térmica. El marco ha de estar integrado en la profundidad del vidrio aislante. En una primera fase se han efectuado cálculos estructurales y térmicos preliminares para evaluar las prestaciones a un nivel esquemático. Además, se han realizado ensayos a flexión en materiales compuestos de fibra de vidrio y ensayos a cortante en las conexiones adhesivas entre vidrio y material compuesto. Con la información obtenida se ha seleccionado el material del marco y del adhesivo y se han efectuado cambios sobre el diseño original. Los análisis numéricos finales demuestran una reducción de la profundidad estructural de un 80% y una reducción de la transmisión térmica de un 6% en comparación con un sistema convencional tomado como referencia. El sistema propuesto permite obtener acabados enrasados. ABSTRACT Unitised curtain wall systems consist of pre manufactured cladding panels which can be fitted to the building via pre fixed brackets along the edge of the floor slab. They are universally used for high rise buildings because the factory controlled assembly of units ensures high quality and allows fast installation without external access. However, its frame is structurally over-dimensioned because it is designed to carry the full structural load, failing to take advantage of potential composite contribution of glass. Subsequently, it is unnecessarily deep, occupying valuable space, and protrudes to the inside, causing visual disruption. Moreover, it is generally made of high thermal conductivity metal alloys, contributing to substantial thermal transmission at joints. This research aims to develop a novel frame-integrated unitised curtain wall system that will reduce thermal transmission at joints, reduce structural depth significantly and allow an inside flush finish. The idea is to adhesively bond a Fibre Reinforced Polymer (FRP) frame to the edge of the Insulated Glass Unit (IGU), thereby achieving composite structural behaviour and low thermal transmittance. The frame is to fit within the glazing cavity depth. Preliminary analytical structural and numerical thermal calculations are carried out to assess the performance of an initial schematic design. 4-point bending tests on GFRP and single-lap shear tests on bonded connections between GFRP and glass are performed to inform the frame and adhesive material selection process and to characterise these materials. Based on the preliminary calculations and experimental tests, some changes are put into effect to improve the performance of the system and mitigate potential issues. Structural and thermal numerical analysis carried out on the final detail design confirm a reduction of the structural depth to almost one fifth and a reduction of thermal transmission of 6% compared to a benchmark conventional system. A flush glazed appearance both to the inside and the outside are provided while keeping the full functionality of a unitised system.