Microfabrication processes for microfluidic devices on a single laser Workstation: direct writing lithography on SU-8, laser ablation on polymers and mask manufacturing

We demonstrate the capability of a laser micromachining workstation for cost-effective manufacturing of a variety of microfluidic devices, including SU-8 microchannels on silicon wafers and 3D complex structures made on polyimide Kapton® or poly carbonate (PC). The workstation combines a KrF excimer laser at 248 nm and a Nd3+:YVO4 DPSS with a frequency tripled at 355 nm with a lens magnification 10X, both lasers working at a pulsed regime with nanoseconds (ns) pulse duration. Workstation also includes a high-resolution motorized XYZ-tilt axis (~ 1 um / axis) and a Through The Lens (TTL) imaging system for a high accurate positioning over a 120 x 120 mm working area. We have surveyed different fabrication techniques: direct writing lithography,mask manufacturing for contact lithography and polymer laser ablation for complex 3D devices, achieving width channels down to 13μ m on 50μ m SU-8 thickness using direct writing lithography, and width channels of 40 μm for polyimide on SiO2 plate. Finally, we have tested the use of some devices for capillary chips measuring the flow speed for liquids with different viscosities. As a result, we have characterized the presence of liquid in the channel by interferometric microscopy.

Contribution to the Analysis, Design and Assessment of Compact Antenna Test Ranges At Millimeter Wavelengths - Contribución al Análisis, Diseño y Caracterización de Sistemas de Medida de Antenas en Rango Compacto para Frecuencias Milimétricas

This Doctoral Thesis entitled Contribution to the analysis, design and assessment of compact antenna test ranges at millimeter wavelengths aims to deepen the knowledge of a particular antenna measurement system: the compact range, operating in the frequency bands of millimeter wavelengths. The thesis has been developed at Radiation Group (GR), an antenna laboratory which belongs to the Signals, Systems and Radiocommunications department (SSR), from Technical University of Madrid (UPM). The Radiation Group owns an extensive experience on antenna measurements, running at present four facilities which operate in different configurations: Gregorian compact antenna test range, spherical near field, planar near field and semianechoic arch system. The research work performed in line with this thesis contributes the knowledge of the first measurement configuration at higher frequencies, beyond the microwaves region where Radiation Group features customer-level performance. To reach this high level purpose, a set of scientific tasks were sequentially carried out. Those are succinctly described in the subsequent paragraphs. A first step dealed with the State of Art review. The study of scientific literature dealed with the analysis of measurement practices in compact antenna test ranges in addition with the particularities of millimeter wavelength technologies. Joint study of both fields of knowledge converged, when this measurement facilities are of interest, in a series of technological challenges which become serious bottlenecks at different stages: analysis, design and assessment. Thirdly after the overview study, focus was set on Electromagnetic analysis algorithms. These formulations allow to approach certain electromagnetic features of interest, such as field distribution phase or stray signal analysis of particular structures when they interact with electromagnetic waves sources. Properly operated, a CATR facility features electromagnetic waves collimation optics which are large, in terms of wavelengths. Accordingly, the electromagnetic analysis tasks introduce an extense number of mathematic unknowns which grow with frequency, following different polynomic order laws depending on the used algorithmia. In particular, the optics configuration which was of our interest consisted on the reflection type serrated edge collimator. The analysis of these devices requires a flexible handling of almost arbitrary scattering geometries, becoming this flexibility the nucleus of the algorithmia’s ability to perform the subsequent design tasks. This thesis’ contribution to this field of knowledge consisted on reaching a formulation which was powerful at the same time when dealing with various analysis geometries and computationally speaking. Two algorithmia were developed. While based on the same principle of hybridization, they reached different order Physics performance at the cost of the computational efficiency. Inter-comparison of their CATR design capabilities was performed, reaching both qualitative as well as quantitative conclusions on their scope. In third place, interest was shifted from analysis - design tasks towards range assessment. Millimetre wavelengths imply strict mechanical tolerances and fine setup adjustment. In addition, the large number of unknowns issue already faced in the analysis stage appears as well in the on chamber field probing stage. Natural decrease of dynamic range available by semiconductor millimeter waves sources requires in addition larger integration times at each probing point. These peculiarities increase exponentially the difficulty of performing assessment processes in CATR facilities beyond microwaves. The bottleneck becomes so tight that it compromises the range characterization beyond a certain limit frequency which typically lies on the lowest segment of millimeter wavelength frequencies. However the value of range assessment moves, on the contrary, towards the highest segment. This thesis contributes this technological scenario developing quiet zone probing techniques which achieves substantial data reduction ratii. Collaterally, it increases the robustness of the results to noise, which is a virtual rise of the setup’s available dynamic range. In fourth place, the environmental sensitivity of millimeter wavelengths issue was approached. It is well known the drifts of electromagnetic experiments due to the dependance of the re sults with respect to the surrounding environment. This feature relegates many industrial practices of microwave frequencies to the experimental stage, at millimeter wavelengths. In particular, evolution of the atmosphere within acceptable conditioning bounds redounds in drift phenomena which completely mask the experimental results. The contribution of this thesis on this aspect consists on modeling electrically the indoor atmosphere existing in a CATR, as a function of environmental variables which affect the range’s performance. A simple model was developed, being able to handle high level phenomena, such as feed - probe phase drift as a function of low level magnitudes easy to be sampled: relative humidity and temperature. With this model, environmental compensation can be performed and chamber conditioning is automatically extended towards higher frequencies. Therefore, the purpose of this thesis is to go further into the knowledge of millimetre wavelengths involving compact antenna test ranges. This knowledge is dosified through the sequential stages of a CATR conception, form early low level electromagnetic analysis towards the assessment of an operative facility, stages for each one of which nowadays bottleneck phenomena exist and seriously compromise the antenna measurement practices at millimeter wavelengths.

Understanding the selective area growth of GaN nanocolumns by MBE using Ti nanomasks

The influence of the substrate temperature, III/V flux ratio, and mask geometry on the selective area growth of GaN nanocolumns is investigated. For a given set of growth conditions, the mask design (diameter and pitch of the nanoholes) is found to be crucial to achieve selective growth within the nanoholes. The local III/V flux ratio within these nanoholes is a key factor that can be tuned, either by modifying the growth conditions or the mask geometry. On the other hand, some specific growth conditions may lead to selective growth but not be suitable for subsequent vertical growth. With optimized conditions, ordered GaN nanocolumns can be grown with a wide variety of diameters. In this work, ordered GaN nanocolumns with diameter as small as 50 nm are shown.

Critical aspects of substrate nanopatterning for the ordered growth of GaN nanocolumns.

Precise and reproducible surface nanopatterning is the key for a successful ordered growth of GaN nanocolumns. In this work, we point out the main technological issues related to the patterning process, mainly surface roughness and cleaning, and mask adhesion to the substrate. We found that each of these factors, process-related, has a dramatic impact on the subsequent selective growth of the columns inside the patterned holes. We compare the performance of e-beam lithography, colloidal lithography, and focused ion beam in the fabrication of hole-patterned masks for ordered columnar growth. These results are applicable to the ordered growth of nanocolumns of different materials.

Selective area growth of a- and c-plane GaN nanocolumns by molecular beam epitaxy using colloidal nanolithography

Selective area growth of a-plane GaN nanocolumns by molecular beam epitaxy was performed for the first time on a-plane GaN templates. Ti masks with 150 nm diameter nanoholes were fabricated by colloidal lithography, an easy, fast and cheap process capable to handle large areas. Even though colloidal lithography does not provide a perfect geometrical arrangement like e-beam lithography, it produces a very homogeneous mask in terms of nanohole diameter and density, and is used here for the first time for the selective area growth of GaN. Selective area growth of a-plane GaN nanocolumns is compared, in terms of anisotropic lateral and vertical growth rates, with GaN nanocolumns grown selectively on the c-plane

Control of the morphology on selective area growth of GaN nanocolumns by rf-plasma-assisted

Selective area growth (SAG) of GaN nanocolumns (NCs), making use of patterned or masked (nanoholes) substrates, yields a periodic, homogeneous distribution of nanostructures, that makes their processing much easier compared with self-assembled ones. In addition, the control on the diameter and density of NCs avoids dispersion in the electrooptical characteristics of the heterostructures based on this type of material (embedded InGaN/GaN quantum disks for example). Selective area growth using a mask with nanohole arrays has been demonstrated by rf-plasma-assisted MBE [1, 2].

ITEM: Inter-Texture Error Measurement for 3D Meshes

We introduce a simple and innovative method to compare any two texture maps, regardless of their sizes, aspect ratios, or even masks, as long as they are both meant to be mapped onto the same 3D mesh. Our system is based on a zero-distortion 3D mesh unwrapping technique which compares two new adapted texture atlases with the same mask but different texel colors, and whose every texel covers the same area in 3D. Once these adapted atlases are created, we measure their difference with ITEM-RMSE, a slightly modified version of the standard RMSE defined for images. ITEM-RMSE is more meaningful and reliable than RMSE because it only takes into account the texels inside the mask, since they are the only ones that will actually be used during rendering. Our method is not only very useful to compare the space efficiency of different texture atlas generation algorithms, but also to quantify texture loss in compression schemes for multi-resolution textured 3D meshes.

Crecimiento, fabricación y caracterización de heteroestructuras y nanocolumnas ordenadas basadas en nitruros del grupo III para aplicaciones sensoras

Esta memoria está basada en el crecimiento y caracterización de heteroestructuras Al(Ga)N/GaN y nanocolumnas ordenadas de GaN, y su aplicación en sensores químicos. El método de crecimiento ha sido la epitaxia de haces moleculares asistida por plasma (PAMBE). En el caso de las heteroestructuras Al(Ga)N/GaN, se han crecido barreras de distinto espesor y composición, desde AlN de 5 nm, hasta AlGaN de 35 nm. Además de una caracterización morfológica, estructural y eléctrica básica de las capas, también se han fabricado a partir de ellas dispositivos tipo HEMTs. La caracterización eléctrica de dichos dispositivos (carga y movilidad de en el canal bidimensional) indica que las mejores heteroestructuras son aquellas con un espesor de barrera intermedio (alrededor de 20 nm). Sin embargo, un objetivo importante de esta Tesis ha sido verificar las ventajas que podían tener los sensores basados en heteroestructuras AlN/GaN (frente a los típicos basados en AlGaN/GaN), con espesores de barrera muy finos (alrededor de 5 nm), ya que el canal de conducción que se modula por efecto de cambios químicos está más cerca de la superficie en donde ocurren dichos cambios químicos. De esta manera, se han utilizado los dispositivos tipo HEMTs como sensores químicos de pH (ISFETs), y se ha comprobado la mayor sensibilidad (variación de corriente frente a cambios de pH, Ids/pH) en los sensores basados en AlN/GaN frente a los basados en AlGaN/GaN. La mayor sensibilidad es incluso más patente en aplicaciones en las que no se utiliza un electrodo de referencia. Se han fabricado y caracterizado dispositivos ISFET similares utilizando capas compactas de InN. Estos sensores presentan peor estabilidad que los basados en Al(Ga)N/GaN, aunque la sensibilidad superficial al pH era la misma (Vgs/pH), y su sensibilidad en terminos de corriente de canal (Ids/pH) arroja valores intermedios entre los ISFET basados en AlN/GaN y los valores de los basados en AlGaN/GaN. Para continuar con la comparación entre dispositivos basados en Al(Ga)N/GaN, se fabricaron ISFETs con el área sensible más pequeña (35 x 35 m2), de tamaño similar a los dispositivos destinados a las medidas de actividad celular. Sometiendo los dispositivos a pulsos de voltaje en su área sensible, la respuesta de los dispositivos de AlN presentaron menor ruido que los basados en AlGaN. El ruido en la corriente para dispositivos de AlN, donde el encapsulado no ha sido optimizado, fue tan bajo como 8.9 nA (valor rms), y el ruido equivalente en el potencial superficial 38.7 V. Estos valores son más bajos que los encontrados en los dispositivos típicos para la detección de actividad celular (basados en Si), y del orden de los mejores resultados encontrados en la literatura sobre AlGaN/GaN. Desde el punto de vista de la caracterización electro-química de las superficies de GaN e InN, se ha determinado su punto isoeléctrico. Dicho valor no había sido reportado en la literatura hasta el momento. El valor, determinado por medidas de “streaming potential”, es de 4.4 y 4 respectivamente. Este valor es una importante característica a tener en cuenta en sensores, en inmovilización electrostática o en la litografía coloidal. Esta última técnica se discute en esta memoria, y se aplica en el último bloque de investigación de esta Tesis (i.e. crecimiento ordenado). El último apartado de resultados experimentales de esta Tesis analiza el crecimiento selectivo de nanocolumnas ordenadas de GaN por MBE, utilizando mascaras de Ti con nanoagujeros. Se ha estudiado como los distintos parámetros de crecimiento (i.e. flujos de los elementos Ga y N, temperatura de crecimiento y diseño de la máscara) afectan a la selectividad y a la morfología de las nanocolumnas. Se ha conseguido con éxito el crecimiento selectivo sobre pseudosustratos de GaN con distinta orientación cristalina o polaridad; templates de GaN(0001)/zafiro, GaN(0001)/AlN/Si, GaN(000-1)/Si y GaN(11-20)/zafiro. Se ha verificado experimentalmente la alta calidad cristalina de las nanocolumnas ordenadas, y su mayor estabilidad térmica comparada con las capas compactas del mismo material. Las nanocolumnas ordenadas de nitruros del grupo III tienen una clara aplicación en el campo de la optoelectrónica, principalmente para nanoemisores de luz blanca. Sin embargo, en esta Tesis se proponen como alternativa a la utilización de capas compactas o nanocolumnas auto-ensambladas en sensores. Las nanocolumnas auto-ensambladas de GaN, debido a su alta razón superficie/volumen, son muy prometedoras en el campo de los sensores, pero su amplia dispersión en dimensiones (altura y diámetro) supone un problema para el procesado y funcionamiento de dispositivos reales. En ese aspecto, las nanocolumnas ordenadas son más robustas y homogéneas, manteniendo una alta relación superficie/volumen. Como primer experimento en el ámbito de los sensores, se ha estudiado como se ve afectada la emisión de fotoluminiscencia de las NCs ordenadas al estar expuestas al aire o al vacio. Se observa una fuerte caída en la intensidad de la fotoluminiscencia cuando las nanocolumnas están expuestas al aire (probablemente por la foto-adsorción de oxigeno en la superficie), como ya había sido documentado anteriormente en nanocolumnas auto-ensambladas. Este experimento abre el camino para futuros sensores basados en nanocolumnas ordenadas. Abstract This manuscript deals with the growth and characterization of Al(Ga)N/GaN heterostructures and GaN ordered nanocolumns, and their application in chemical sensors. The growth technique has been the plasma-assisted molecular beam epitaxy (PAMBE). In the case of Al(Ga)N/GaN heterostructures, barriers of different thickness and composition, from AlN (5 nm) to AlGaN (35 nm) have been grown. Besides the basic morphological, structural and electrical characterization of the layers, HEMT devices have been fabricated based on these layers. The best electrical characteristics (larger carriers concentration and mobility in the two dimensional electron gas) are those in AlGaN/GaN heterostructures with a medium thickness (around 20 nm). However, one of the goals of this Thesis has been to verify the advantages that sensors based on AlN/GaN (thickness around 7 nm) have compared to standard AlGaN/GaN, because the conduction channel to be modulated by chemical changes is closer to the sensitive area. In this way, HEMT devices have been used as chemical pH sensors (ISFETs), and the higher sensitivity (conductance change related to pH changes, Ids/pH) of AlN/GaN based sensors has been proved. The higher sensibility is even more obvious in application without reference electrode. Similar ISFETs devices have been fabricated based on InN compact layers. These devices show a poor stability, but its surface sensitivity to pH (Vgs/pH) and its sensibility (Ids/pH) yield values between the corresponding ones of AlN/GaN and AlGaN/GaN heterostructures. In order to a further comparison between Al(Ga)N/GaN based devices, ISFETs with smaller sensitive area (35 x 35 m2), similar to the ones used in cellular activity record, were fabricated and characterized. When the devices are subjected to a voltage pulse through the sensitive area, the response of AlN based devices shows lower noise than the ones based on AlGaN. The noise in the current of such a AlN based device, where the encapsulation has not been optimized, is as low as 8.9 nA (rms value), and the equivalent noise to the surface potential is 38.7 V. These values are lower than the found in typical devices used for cellular activity recording (based on Si), and in the range of the best published results on AlGaN/GaN. From the point of view of the electrochemical characterization of GaN and InN surfaces, their isoelectric point has been experimentally determined. Such a value is the first time reported for GaN and InN surfaces. These values are determined by “streaming potential”, being pH 4.4 and 4, respectively. Isoelectric point value is an important characteristic in sensors, electrostatic immobilization or in colloidal lithography. In particular, colloidal lithography has been optimized in this Thesis for GaN surfaces, and applied in the last part of experimental results (i.e. ordered growth). The last block of this Thesis is focused on the selective area growth of GaN nanocolumns by MBE, using Ti masks decorated with nanoholes. The effect of the different growth parameters (Ga and N fluxes, growth temperature and mask design) is studied, in particular their impact in the selectivity and in the morphology of the nanocolumns. Selective area growth has been successful performed on GaN templates with different orientation or polarity; GaN(0001)/sapphire, GaN(0001)/AlN/Si, GaN(000- 1)/Si and GaN(11-20)/sapphire. Ordered nanocolumns exhibit a high crystal quality, and a higher thermal stability (lower thermal decomposition) than the compact layers of the same material. Ordered nanocolumns based on III nitrides have a clear application in optoelectronics, mainly for white light nanoemitters. However, this Thesis proposes them as an alternative to compact layers and self-assembled nanocolumns in sensor applications. Self-assembled GaN nanocolumns are very appealing for sensor applications, due to their large surface/volume ratio. However, their large dispersion in heights and diameters are a problem in terms of processing and operation of real devices. In this aspect, ordered nanocolumns are more robust and homogeneous, keeping the large surface/volume ratio. As first experimental evidence of their sensor capabilities, ordered nanocolumns have been studied regarding their photoluminiscence on air and vacuum ambient. A big drop in the intensity is observed when the nanocolumns are exposed to air (probably because of the oxygen photo-adsortion), as was already reported in the case of self-assembled nanocolumns. This opens the way to future sensors based on ordered III nitrides nanocolumns.

Electrooptic characterization of tunable cylindrical liquid crystal lenses

In this work, one-dimensional arrays of cylindrical adaptive liquid crystal lenses were manufactured and characterized; and test devices were filled with nematic liquid crystal. Comb interdigitated electrodes were designed as a mask pattern for the control electrode on the top glass substrates. A radial graded refractive index along each microsized lens was achieved by fabricating a layer of high resistance sheet deposited as a control electrode. These tunable lenses were switched by applying amplitude and frequency optimized waveforms on the control electrode. Phase profiles generated by the radial electric field distribution on each lens were measured by a convectional interferometric technique.

Methodology for registration of distended recutms in pelvic CT studies

Purpose: Accurate delineation of the rectum is of high importance in off-line adaptive radiation therapy since it is a major dose-limiting organ in prostate cancer radiotherapy. The intensity-based deformable image registration (DIR) methods cannot create a correct spatial transformation if there is no correspondence between the template and the target images. The variation of rectal filling, gas, or feces, creates a noncorrespondence in image intensities that becomes a great obstacle for intensity-based DIR. Methods: In this study the authors have designed and implemented a semiautomatic method to create a rectum mask in pelvic computed tomography (CT) images. The method, that includes a DIR based on the demons algorithm, has been tested in 13 prostate cancer cases, each comprising of two CT scans, for a total of 26 CT scans. Results: The use of the manual segmentation in the planning image and the proposed rectum mask method (RMM) method in the daily image leads to an improvement in the DIR performance in pelvic CT images, obtaining a mean value of overlap volume index = 0.89, close to the values obtained using the manual segmentations in both images. Conclusions: The application of the RMM method in the daily image and the manual segmentations in the planning image during prostate cancer treatments increases the performance of the registration in presence of rectal fillings, obtaining very good agreement with a physician's manual contours.

E-beam nano-patterning for the ordered growth of GaN/InGaN nanorods

E-beam lithography was used to pattern a titanium mask on a GaN substrate with ordered arrays of nanoholes. This patterned mask served as a template for the subsequent ordered growth of GaN/InGaN nanorods by plasma-assisted molecular beam epitaxy. The mask patterning process was optimized for several holes configurations. The smallest holes were 30 nm in diameter with a pitch (center-to-center distance) of 100 nm only. High quality masks of several geometries were obtained that could be used to grow ordered GaN/InGaN nanorods with full selectivity (growth localized inside the nanoholes only) over areas of hundreds of microns. Although some parasitic InGaN growth occurred between the nanorods during the In incorporation, transmission electron microscopy and photoluminescence measurements demonstrated that these ordered nanorods exhibit high crystal quality and reproducible optical properties.

Methodology for registration of distended rectums in pelvic CT studies

Purpose: Accurate delineation of the rectum is of high importance in off-line adaptive radiation therapy since it is a major dose-limiting organ in prostate cancer radiotherapy. The intensity-based deformable image registration (DIR) methods cannot create a correct spatial transformation if there is no correspondence between the template and the target images. The variation of rectal filling, gas, or feces, creates a noncorrespondence in image intensities that becomes a great obstacle for intensity-based DIR. Methods: In this study the authors have designed and implemented a semiautomatic method to create a rectum mask in pelvic computed tomography (CT) images. The method, that includes a DIR based on the demons algorithm, has been tested in 13 prostate cancer cases, each comprising of two CT scans, for a total of 26 CT scans. Results: The use of the manual segmentation in the planning image and the proposed rectum mask method (RMM) method in the daily image leads to an improvement in the DIR performance in pelvic CT images, obtaining a mean value of overlap volume index = 0.89, close to the values obtained using the manual segmentations in both images. Conclusions: The application of the RMM method in the daily image and the manual segmentations in the planning image during prostate cancer treatments increases the performance of the registration in presence of rectal fillings, obtaining very good agreement with a physician's manual contours.

Full-Wafer Roller-NIL Processes for Silicon Solar Cell Texturisation

The highest solar cell efficiencies both for c-Si and mc-Si were reached using template based texturing processes. Especially for mc-Si the benefit of a defined texture, the so called honeycomb texture, was demonstrated impressively. However, up until now, no industrially feasible process has been available to pattern the necessary etching masks with the sufficient resolution. Roller-Nanoimprint Lithography (Roller-NIL) has the potential to overcome these limitations and to allow high quality pattern transfers, even in the sub-micron regime, in continuous in-line processes. Therefore, this etch-mask patterning technique is a suitable solution to bring such elaborate features like the honeycomb texture to an industrial realization. Beyond that, this fast printing-like technology opens up new possibilities to introduce promising concepts like photonic structures into solar cells.

Optical digital chaos cryptography

In this work we present a new way to mask the data in a one-user communication system when direct sequence - code division multiple access (DS-CDMA) techniques are used. The code is generated by a digital chaotic generator, originally proposed by us and previously reported for a chaos cryptographic system. It is demonstrated that if the user's data signal is encoded with a bipolar phase-shift keying (BPSK) technique, usual in DS-CDMA, it can be easily recovered from a time-frequency domain representation. To avoid this situation, a new system is presented in which a previous dispersive stage is applied to the data signal. A time-frequency domain analysis is performed, and the devices required at the transmitter and receiver end, both user-independent, are presented for the optical domain.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.