Energy/power consumption model for an embedded processor board

This dissertation, whose research has been conducted at the Group of Electronic and Microelectronic Design (GDEM) within the framework of the project Power Consumption Control in Multimedia Terminals (PCCMUTE), focuses on the development of an energy estimation model for the battery-powered embedded processor board. The main objectives and contributions of the work are summarized as follows: A model is proposed to obtain the accurate energy estimation results based on the linear correlation between the performance monitoring counters (PMCs) and energy consumption. the uniqueness of the appropriate PMCs for each different system, the modeling methodology is improved to obtain stable accuracies with slight variations among multiple scenarios and to be repeatable in other systems. It includes two steps: the former, the PMC-filter, to identify the most proper set among the available PMCs of a system and the latter, the k-fold cross validation method, to avoid the bias during the model training stage. The methodology is implemented on a commercial embedded board running the 2.6.34 Linux kernel and the PAPI, a cross-platform interface to configure and access PMCs. The results show that the methodology is able to keep a good stability in different scenarios and provide robust estimation results with the average relative error being less than 5%. Este trabajo fin de máster, cuya investigación se ha desarrollado en el Grupo de Diseño Electrónico y Microelectrónico (GDEM) en el marco del proyecto PccMuTe, se centra en el desarrollo de un modelo de estimación de energía para un sistema empotrado alimentado por batería. Los objetivos principales y las contribuciones de esta tesis se resumen como sigue: Se propone un modelo para obtener estimaciones precisas del consumo de energía de un sistema empotrado. El modelo se basa en la correlación lineal entre los valores de los contadores de prestaciones y el consumo de energía. Considerando la particularidad de los contadores de prestaciones en cada sistema, la metodología de modelado se ha mejorado para obtener precisiones estables, con ligeras variaciones entre escenarios múltiples y para replicar los resultados en diferentes sistemas. La metodología incluye dos etapas: la primera, filtrado-PMC, que consiste en identificar el conjunto más apropiado de contadores de prestaciones de entre los disponibles en un sistema y la segunda, el método de validación cruzada de K iteraciones, cuyo fin es evitar los sesgos durante la fase de entrenamiento. La metodología se implementa en un sistema empotrado que ejecuta el kernel 2.6.34 de Linux y PAPI, un interfaz multiplataforma para configurar y acceder a los contadores. Los resultados muestran que esta metodología consigue una buena estabilidad en diferentes escenarios y proporciona unos resultados robustos de estimación con un error medio relativo inferior al 5%.

Reducing the impact of EV charging on the electric grid

One of the main objectives of European Commission related to climate and energy is the well-known 20-20-20 targets to be achieved in 2020: Europe has to reduce greenhouse gas emissions of at least 20% below 1990 levels, 20% of EU energy consumption has to come from renewable resources and, finally, a 20% reduction in primary energy use compared with projected levels, has to be achieved by improving energy efficiency. In order to reach these objectives, it is necessary to reduce the overall emissions, mainly in transport (reducing CO2, NOx and other pollutants), and to increase the penetration of the intermittent renewable energy. A high deployment of battery electric (BEVs) and plug-in hybrid electric vehicles (PHEVs), with a low-cost source of energy storage, could help to achieve both targets. Hybrid electric vehicles (HEVs) use a combination of a conventional internal combustion engine (ICE) with one (or more) electric motor. There are different grades of hybridation from micro-hybrids with start-stop capability, mild hybrids (with kinetic energy recovery), medium hybrids (mild hybrids plus energy assist) and full hybrids (medium hybrids plus electric launch capability). These last types of vehicles use a typical battery capacity around 1-2 kWh. Plug in hybrid electric vehicles (PHEVs) use larger battery capacities to achieve limited electric-only driving range. These vehicles are charged by on-board electricity generation or either plugging into electric outlets. Typical battery capacity is around 10 kWh. Battery Electric Vehicles (BEVs) are only driven by electric power and their typical battery capacity is around 15-20 kWh. One type of PHEV, the Extended Range Electric Vehicle (EREV), operates as a BEV until its plug-in battery capacity is depleted; at which point its gasoline engine powers an electric generator to extend the vehicle's range. The charging of PHEVs (including EREVs) and BEVs will have different impacts to the electric grid, depending on the number of vehicles and the start time for charging. Initially, the lecture will start analyzing the electrical power requirements for charging PHEVs-BEVs in Flanders region (Belgium) under different charging scenarios. Secondly and based on an activity-based microsimulation mobility model, an efficient method to reduce this impact will be presented.

A low power routing algorithm for localization in IEEE 802.15.4 networks

Many context-aware applications rely on the knowledge of the position of the user and the surrounding objects to provide advanced, personalized and real-time services. In wide-area deployments, a routing protocol is needed to collect the location information from distant nodes. In this paper, we propose a new source-initiated (on demand) routing protocol for location-aware applications in IEEE 802.15.4 wireless sensor networks. This protocol uses a low power MAC layer to maximize the lifetime of the network while maintaining the communication delay to a low value. Its performance is assessed through experimental tests that show a good trade-off between power consumption and time delay in the localization of a mobile device.

Ultra Low Power FPGA-Based Architecture for Wake-up Radio in Wireless Sensor Networks

In this paper the capabilities of ultra low power FPGAs to implement Wake-up Radios (WuR) for ultra low energy Wireless Sensor Networks (WSNs) are analyzed. The main goal is to evaluate the utilization of very low power configurable devices to take advantage of their speed, flexibility and low power consumption instead of the more common approaches based on ASICs or microcontrollers. In this context, energy efficiency is a key aspect, considering that usually the instant power consumption is considered a figure of merit, more than the total energy consumed by the application.

Wake up Radio Architecture for Wireless Sensor Networks Using an Ultra Low Power FPGA

In this paper an implementation of a Wake up Radio(WuR) with addressing capabilities based on an ultra low power FPGA for ultra low energy Wireless Sensor Networks (WSNs) is proposed. The main goal is to evaluate the utilization of very low power configurable devices to take advantage of their speed, flexibility and low power consumption instead of the traditional approaches based on ASICs or microcontrollers, for communication frame decoding and communication data control.

Low-power, high-speed FFT processor for MB-OFDM UWB application

This paper presents a low-power, high-speed 4-data-path 128-point mixed-radix (radix-2 & radix-2 2 ) FFT processor for MB-OFDM Ultra-WideBand (UWB) systems. The processor employs the single-path delay feedback (SDF) pipelined structure for the proposed algorithm, it uses substructure-sharing multiplication units and shift-add structure other than traditional complex multipliers. Furthermore, the word lengths are properly chosen, thus the hardware costs and power consumption of the proposed FFT processor are efficiently reduced. The proposed FFT processor is verified and synthesized by using 0.13 µm CMOS technology with a supply voltage of 1.32 V. The implementation results indicate that the proposed 128-point mixed-radix FFT architecture supports a throughput rate of 1Gsample/s with lower power consumption in comparison to existing 128-point FFT architectures

SMA-Based Muscle-Like Actuation in Biologically Inspired Robots: A State of the Art Review

New actuation technology in functional or "smart" materials has opened new horizons in robotics actuation systems. Materials such as piezo-electric fiber composites, electro-active polymers and shape memory alloys (SMA) are being investigated as promising alternatives to standard servomotor technology [52]. This paper focuses on the use of SMAs for building muscle-like actuators. SMAs are extremely cheap, easily available commercially and have the advantage of working at low voltages. The use of SMA provides a very interesting alternative to the mechanisms used by conventional actuators. SMAs allow to drastically reduce the size, weight and complexity of robotic systems. In fact, their large force-weight ratio, large life cycles, negligible volume, sensing capability and noise-free operation make possible the use of this technology for building a new class of actuation devices. Nonetheless, high power consumption and low bandwidth limit this technology for certain kind of applications. This presents a challenge that must be addressed from both materials and control perspectives in order to overcome these drawbacks. Here, the latter is tackled. It has been demonstrated that suitable control strategies and proper mechanical arrangements can dramatically improve on SMA performance, mostly in terms of actuation speed and limit cycles.

Wake-up architecture for Wireless sensor nodes based on ultra low power FPGA

In this work a novel wake-up architecture for wireless sensor nodes based on ultra low power FPGA is presented. A simple wake up messaging mechanism for data gathering applications is proposed. The main goal of this work is to evaluate the utilization of low power configurable devices to take advantage of their speed, flexibility and low power consumption compared with traditional approaches, based on ASICs or microcontrollers, for frame decoding and data control. A test bed based on infrared communications has been built to validate the messaging mechanism and the processing architecture.

Integración de baterías en sistemas fotovoltaicos conectados a red

La situación actual del mercado energético en España y el imparable aumento de las tasas por parte de las eléctricas, está fomentando la búsqueda de fuentes de energía alternativas que permitan a la población poder abastecerse de electricidad, sin tener que pagar unos costes tan elevados. Para cubrir esta necesidad, la energía fotovoltaica y sobretodo el autoconsumo con inyección a red o balance neto, está adquiriendo cada vez más importancia dentro del mundo energético. Pero la penetración de esta tecnología en la Red Eléctrica Española tiene un freno, la desconfianza por parte del operador de la red, ya que la fotovoltaica es una fuente de energía intermitente, que puede introducir inestabilidades en el sistema en caso de alta penetración. Por ello se necesita ganar la confianza de las eléctricas, haciendo que sea una energía predecible, que aporte potencia a la red eléctrica cuando se le pida y que opere participando en la regulación de la frecuencia del sistema eléctrico. Para tal fin, el grupo de investigación de Sistemas Fotovoltaicos, perteneciente al IES de la UPM, está llevando a cabo un proyecto de investigación denominado PV CROPS, financiado por la Comisión Europea, y que tiene por objetivo desarrollar estas estrategias de gestión. En este contexto, el objetivo de este Proyecto Fin de Carrera consiste en implementar un Banco de Ensayos con Integración de Baterías en Sistemas FV Conectados a Red, que permita desarrollar, ensayar y validar estas estrategias. Aprovechando la disponibilidad para usar el Hogar Digital, instalado en la EUITT de la UPM, hemos montado el banco de ensayos en un laboratorio contiguo, y así, poder utilizar este Hogar como un caso real de consumos energéticos de una vivienda. Este banco de ensayos permitirá obtener información de la energía generada por la instalación fotovoltaica y del consumo real de la "casa" anexa, para desarrollar posteriormente estrategias de gestión de la electricidad. El Banco de Ensayos está compuesto por tres bloques principales, interconectados entre sí:  Subsistema de Captación de Datos y Comunicación. Encargado de monitorizar los elementos energéticos y de enviar la información recopilada al Subsistema de Control. Formado por analizadores de red eléctrica, monofásicos y de continua, y una pasarela orientada a la conversión del medio físico Ethernet a RS485.  Subsistema de Control. Punto de observación y recopilación de toda la información que proviene de los elementos energéticos. Es el subsistema donde se crearán y se implementarán estrategias de control energético. Compuesto por un equipo Pxie, controlador empotrado en un chasis de gama industrial, y un equipo PC Host, compuesto por una workstation y tres monitores.  Subsistema de Energía. Formado por los elementos que generan, controlan o consumen energía eléctrica, en el Banco de Ensayos. Constituido por una pérgola FV, un inversor, un inversor bidireccional y un bloque de baterías. El último paso ha sido llevar a cabo un Ejemplo de Aplicación Práctica, con el que hemos probado que el Banco de Ensayos está listo para usarse, es operativo y completamente funcional en operaciones de monitorización de generación energética fotovoltaica y consumo energético. ABSTRACT. The current situation of the energetic market in Spain and the unstoppable increase of the tax on the part of the electrical companies, is promoting the search of alternative sources of energy that allow to the population being able to be supplied of electricity, without having to pay so high costs. To meet this need, the photovoltaic power and above all the self-consumption with injection to network, it is increasingly important inside the energetic world. It allows to the individual not only to pay less for the electricity, in addition it allows to obtain benefits for the energy generated in his own home. But the penetration of this technology in the Electrical Spanish Network has an obstacle, the distrust on the part of the operator of the electrical network, due to the photovoltaic is an intermittent source of energy, which can introduce instabilities in the system in case of high penetration. Therefore it´s necessary to reach the confidence of the electricity companies, making it a predictable energy, which provides with power to the electrical network whenever necessary and that operates taking part in the regulation of the frequency of the electric system. For such an end, the group of system investigation Photovoltaic, belonging to the IES of the UPM, there is carrying out a project of investigation named PV CROPS, financed by the European Commission, and that has for aim to develop these strategies of management. In this context, the objective of this Senior Thesis consists in implementing a Bank of Tests with Integration of Batteries in Photovoltaic Systems Connected to Network, which allows developing, testing and validating these strategies. Taking advantage of the availability to use the Digital Home installed in the EUITT of the UPM, we have mounted the bank of tests in a contiguous laboratory to use this Home as a real case of energetic consumptions of a house. This bank of tests will allow obtaining information of the energy generated by the photovoltaic installation and information of the royal consumption of the attached "house", to develop later strategies of management of the electricity. The Bank of Tests is composed by three principal blocks, interconnected each other:  Subsystem of Gathering of data and Communication. In charge of monitoring the energetic elements and sending the information compiled to the Subsystem of Control. Formed by power analyzers, AC and DC, and a gateway for the conversion of the Ethernet physical medium to RS485.  Subsystem of Control. Point of observation and compilation of all the information that comes from the energetic elements. It is the subsystem where there will be created and there will be implemented strategies of energetic control. Composed of a Pxie, controller fixed in an industrial range chassis, and a PC Host, formed by a workstation and three monitors.  Subsystem of Energy. Formed by the elements of generating, controlling or consuming electric power, in the Bank of Tests. Made of photovoltaic modules, an inverter, a twoway inverter and a batteries block. The last step has been performing an Example of Practical Application we have proved that the Bank of Tests is ready to be used, it´s operative and fully functional in monitoring operations of energetic photovoltaic generation and energetic consumption.

A low-area reference-free power supply sensor

Power supply unpredictable uctuations jeopardize the functioning of several types of current electronic systems. This work presents a power supply sensor based on a voltage divider followed by buffer-comparator cells employing just MOSFET transistors and provides a digital output. The divider outputs are designed to change more slowly than the thresholds of the comparators, in this way the sensor is able to detect voltage droops. The sensor is implemented in a 65nm technology node occupying an area of 2700?m2 and displaying a power consumption of 50?W. It is designed to work with no voltage reference and with no clock and aiming to obtain a fast response.

On the leakage-power modeling for optimal server operation

Leakage power consumption is a com- ponent of the total power consumption in data cen- ters that is not traditionally considered in the set- point temperature of the room. However, the effect of this power component, increased with temperature, can determine the savings associated with the careful management of the cooling system, as well as the re- liability of the system. The work presented in this paper detects the need of addressing leakage power in order to achieve substantial savings in the energy consumption of servers. In particular, our work shows that, by a careful detection and management of two working regions (low and high impact of thermal- dependent leakage), energy consumption of the data- center can be optimized by a reduction of the cooling budget.

On the simulation of the UPMSAT-2 microsatellite power

Simulation of satellite subsystems behaviour is extramely important in the design at early stages. The subsystems are normally simulated in the both ways : isolated and as part of more complex simulation that takes into account imputs from other subsystems (concurrent design). In the present work, a simple concurrent simulation of the power subsystem of a microsatellite, UPMSat-2, is described. The aim of the work is to obtain the performance profile of the system (battery charging level, power consumption by the payloads, power supply from solar panels....). Different situations such as battery critical low or high level, effects of high current charging due to the low temperature of solar panels after eclipse,DoD margins..., were analysed, and different safety strategies studied using the developed tool (simulator) to fulfil the mission requirements. Also, failure cases were analysed in order to study the robustness of the system. The mentioned simulator has been programed taking into account the power consumption performances (average and maximum consumptions per orbit/day) of small part of the subsystem (SELEX GALILEO SPVS modular generators built with Azur Space solar cells, SAFT VES16 6P4S Li-ion battery, SSBV magnetometers, TECNOBIT and DATSI/UPM On Board Data Handling -OBDH-...). The developed tool is then intended to be a modular simulator, with the chance of use any other components implementing some standard data.

Planta de trigeneración para industria papelera

El alcance de este proyecto es dimensionar un sistema de trigeneración para una industria papelera. El proyecto se realizará en base a la propuesta de la nueva reforma de la ley energética, por la cual no se podrá vender la energía eléctrica generada a la red sino que toda la energía generada ha de ser utilizada de forma exclusiva para autoconsumo. En primer lugar se desarrolla un proceso de selección de los equipos y tecnologías para la cogeneración, que posteriormente servirá para el dimensionamiento de la planta, en el cual se elegirá la tecnología oportuna para la generación de energía eléctrica y energía térmica, tanto en forma de frío como de calor. Con este estudio se podrá calcular el ahorro conseguido por el nuevo sistema propuesto, comparado con los costes de la generación por sistemas convencionales y desde ese ahorro, analizar la rentabilidad y viabilidad del proyecto en función de la inversión inicial que supone dicho proyecto. Abstract The scope of this project is to measure a trigeneration system for paper industry. The project will be based on the proposal of the new reform of the energy law, by which the electricity generated to the network may not be sold but that all the generated energy has to be used exclusively for self-consumption. First of all the study develops a process of selection of the equipment and technologies for cogeneration, which subsequently will be used for the dimensioning of the plant, the result will be an election of the appropriate technology for the generation of electric power and heat energy, both in the form of cold and heat. With this study the savings achieved by the new proposed system will be estimated, compared with costs of conventional generation and from these savings, analized for profitability and viability of the project on the basis of the initial investment involved in this project.

Technology and characterization of GaN-HEMTs devices: high temperature and trapping effects

Los transistores de alta movilidad electrónica basados en GaN han sido objeto de una extensa investigación ya que tanto el GaN como sus aleaciones presentan unas excelentes propiedades eléctricas (alta movilidad, elevada concentración de portadores y campo eléctrico crítico alto). Aunque recientemente se han incluido en algunas aplicaciones comerciales, su expansión en el mercado está condicionada a la mejora de varios asuntos relacionados con su rendimiento y habilidad. Durante esta tesis se han abordado algunos de estos aspectos relevantes; por ejemplo, la fabricación de enhancement mode HEMTs, su funcionamiento a alta temperatura, el auto calentamiento y el atrapamiento de carga. Los HEMTs normalmente apagado o enhancement mode han atraído la atención de la comunidad científica dedicada al desarrollo de circuitos amplificadores y conmutadores de potencia, ya que su utilización disminuiría significativamente el consumo de potencia; además de requerir solamente una tensión de alimentación negativa, y reducir la complejidad del circuito y su coste. Durante esta tesis se han evaluado varias técnicas utilizadas para la fabricación de estos dispositivos: el ataque húmedo para conseguir el gate-recess en heterostructuras de InAl(Ga)N/GaN; y tratamientos basados en flúor (plasma CF4 e implantación de F) de la zona debajo de la puerta. Se han llevado a cabo ataques húmedos en heteroestructuras de InAl(Ga)N crecidas sobre sustratos de Si, SiC y zafiro. El ataque completo de la barrera se consiguió únicamente en las muestras con sustrato de Si. Por lo tanto, se puede deducir que la velocidad de ataque depende de la densidad de dislocaciones presentes en la estructura, ya que el Si presenta un peor ajuste del parámetro de red con el GaN. En relación a los tratamientos basados en flúor, se ha comprobado que es necesario realizar un recocido térmico después de la fabricación de la puerta para recuperar la heteroestructura de los daños causados durante dichos tratamientos. Además, el estudio de la evolución de la tensión umbral con el tiempo de recocido ha demostrado que en los HEMTs tratados con plasma ésta tiende a valores más negativos al aumentar el tiempo de recocido. Por el contrario, la tensión umbral de los HEMTs implantados se desplaza hacia valores más positivos, lo cual se atribuye a la introducción de iones de flúor a niveles más profundos de la heterostructura. Los transistores fabricados con plasma presentaron mejor funcionamiento en DC a temperatura ambiente que los implantados. Su estudio a alta temperatura ha revelado una reducción del funcionamiento de todos los dispositivos con la temperatura. Los valores iniciales de corriente de drenador y de transconductancia medidos a temperatura ambiente se recuperaron después del ciclo térmico, por lo que se deduce que dichos efectos térmicos son reversibles. Se han estudiado varios aspectos relacionados con el funcionamiento de los HEMTs a diferentes temperaturas. En primer lugar, se han evaluado las prestaciones de dispositivos de AlGaN/GaN sobre sustrato de Si con diferentes caps: GaN, in situ SiN e in situ SiN/GaN, desde 25 K hasta 550 K. Los transistores con in situ SiN presentaron los valores más altos de corriente drenador, transconductancia, y los valores más bajos de resistencia-ON, así como las mejores características en corte. Además, se ha confirmado que dichos dispositivos presentan gran robustez frente al estrés térmico. En segundo lugar, se ha estudiado el funcionamiento de transistores de InAlN/GaN con diferentes diseños y geometrías. Dichos dispositivos presentaron una reducción casi lineal de los parámetros en DC en el rango de temperaturas de 25°C hasta 225°C. Esto se debe principalmente a la dependencia térmica de la movilidad electrónica, y también a la reducción de la drift velocity con la temperatura. Además, los transistores con mayores longitudes de puerta mostraron una mayor reducción de su funcionamiento, lo cual se atribuye a que la drift velocity disminuye más considerablemente con la temperatura cuando el campo eléctrico es pequeño. De manera similar, al aumentar la distancia entre la puerta y el drenador, el funcionamiento del HEMT presentó una mayor reducción con la temperatura. Por lo tanto, se puede deducir que la degradación del funcionamiento de los HEMTs causada por el aumento de la temperatura depende tanto de la longitud de la puerta como de la distancia entre la puerta y el drenador. Por otra parte, la alta densidad de potencia generada en la región activa de estos transistores conlleva el auto calentamiento de los mismos por efecto Joule, lo cual puede degradar su funcionamiento y Habilidad. Durante esta tesis se ha desarrollado un simple método para la determinación de la temperatura del canal basado en medidas eléctricas. La aplicación de dicha técnica junto con la realización de simulaciones electrotérmicas han posibilitado el estudio de varios aspectos relacionados con el autocalentamiento. Por ejemplo, se han evaluado sus efectos en dispositivos sobre Si, SiC, y zafiro. Los transistores sobre SiC han mostrado menores efectos gracias a la mayor conductividad térmica del SiC, lo cual confirma el papel clave que desempeña el sustrato en el autocalentamiento. Se ha observado que la geometría del dispositivo tiene cierta influencia en dichos efectos, destacando que la distribución del calor generado en la zona del canal depende de la distancia entre la puerta y el drenador. Además, se ha demostrado que la temperatura ambiente tiene un considerable impacto en el autocalentamiento, lo que se atribuye principalmente a la dependencia térmica de la conductividad térmica de las capas y sustrato que forman la heterostructura. Por último, se han realizado numerosas medidas en pulsado para estudiar el atrapamiento de carga en HEMTs sobre sustratos de SiC con barreras de AlGaN y de InAlN. Los resultados obtenidos en los transistores con barrera de AlGaN han presentado una disminución de la corriente de drenador y de la transconductancia sin mostrar un cambio en la tensión umbral. Por lo tanto, se puede deducir que la posible localización de las trampas es la región de acceso entre la puerta y el drenador. Por el contrario, la reducción de la corriente de drenador observada en los dispositivos con barrera de InAlN llevaba asociado un cambio significativo en la tensión umbral, lo que implica la existencia de trampas situadas en la zona debajo de la puerta. Además, el significativo aumento del valor de la resistencia-ON y la degradación de la transconductancia revelan la presencia de trampas en la zona de acceso entre la puerta y el drenador. La evaluación de los efectos del atrapamiento de carga en dispositivos con diferentes geometrías ha demostrado que dichos efectos son menos notables en aquellos transistores con mayor longitud de puerta o mayor distancia entre puerta y drenador. Esta dependencia con la geometría se puede explicar considerando que la longitud y densidad de trampas de la puerta virtual son independientes de las dimensiones del dispositivo. Finalmente se puede deducir que para conseguir el diseño óptimo durante la fase de diseño no sólo hay que tener en cuenta la aplicación final sino también la influencia que tiene la geometría en los diferentes aspectos estudiados (funcionamiento a alta temperatura, autocalentamiento, y atrapamiento de carga). ABSTRACT GaN-based high electron mobility transistors have been under extensive research due to the excellent electrical properties of GaN and its related alloys (high carrier concentration, high mobility, and high critical electric field). Although these devices have been recently included in commercial applications, some performance and reliability issues need to be addressed for their expansion in the market. Some of these relevant aspects have been studied during this thesis; for instance, the fabrication of enhancement mode HEMTs, the device performance at high temperature, the self-heating and the charge trapping. Enhancement mode HEMTs have become more attractive mainly because their use leads to a significant reduction of the power consumption during the stand-by state. Moreover, they enable the fabrication of simpler power amplifier circuits and high-power switches because they allow the elimination of negativepolarity voltage supply, reducing significantly the circuit complexity and system cost. In this thesis, different techniques for the fabrication of these devices have been assessed: wet-etching for achieving the gate-recess in InAl(Ga)N/GaN devices and two different fluorine-based treatments (CF4 plasma and F implantation). Regarding the wet-etching, experiments have been carried out in InAl(Ga)N/GaN grown on different substrates: Si, sapphire, and SiC. The total recess of the barrier was achieved after 3 min of etching in devices grown on Si substrate. This suggests that the etch rate can critically depend on the dislocations present in the structure, since the Si exhibits the highest mismatch to GaN. Concerning the fluorine-based treatments, a post-gate thermal annealing was required to recover the damages caused to the structure during the fluorine-treatments. The study of the threshold voltage as a function of this annealing time has revealed that in the case of the plasma-treated devices it become more negative with the time increase. On the contrary, the threshold voltage of implanted HEMTs showed a positive shift when the annealing time was increased, which is attributed to the deep F implantation profile. Plasma-treated HEMTs have exhibited better DC performance at room temperature than the implanted devices. Their study at high temperature has revealed that their performance decreases with temperature. The initial performance measured at room temperature was recovered after the thermal cycle regardless of the fluorine treatment; therefore, the thermal effects were reversible. Thermal issues related to the device performance at different temperature have been addressed. Firstly, AlGaN/GaN HEMTs grown on Si substrate with different cap layers: GaN, in situ SiN, or in situ SiN/GaN, have been assessed from 25 K to 550 K. In situ SiN cap layer has been demonstrated to improve the device performance since HEMTs with this cap layer have exhibited the highest drain current and transconductance values, the lowest on-resistance, as well as the best off-state characteristics. Moreover, the evaluation of thermal stress impact on the device performance has confirmed the robustness of devices with in situ cap. Secondly, the high temperature performance of InAlN/GaN HEMTs with different layouts and geometries have been assessed. The devices under study have exhibited an almost linear reduction of the main DC parameters operating in a temperature range from room temperature to 225°C. This was mainly due to the thermal dependence of the electron mobility, and secondly to the drift velocity decrease with temperature. Moreover, HEMTs with large gate length values have exhibited a great reduction of the device performance. This was attributed to the greater decrease of the drift velocity for low electric fields. Similarly, the increase of the gate-to-drain distance led to a greater reduction of drain current and transconductance values. Therefore, this thermal performance degradation has been found to be dependent on both the gate length and the gate-to-drain distance. It was observed that the very high power density in the active region of these transistors leads to Joule self-heating, resulting in an increase of the device temperature, which can degrade the device performance and reliability. A simple electrical method have been developed during this work to determine the channel temperature. Furthermore, the application of this technique together with the performance of electro-thermal simulations have enabled the evaluation of different aspects related to the self-heating. For instance, the influence of the substrate have been confirmed by the study of devices grown on Si, SiC, and Sapphire. HEMTs grown on SiC substrate have been confirmed to exhibit the lowest self-heating effects thanks to its highest thermal conductivity. In addition to this, the distribution of the generated heat in the channel has been demonstrated to be dependent on the gate-to-drain distance. Besides the substrate and the geometry of the device, the ambient temperature has also been found to be relevant for the self-heating effects, mainly due to the temperature-dependent thermal conductivity of the layers and the substrate. Trapping effects have been evaluated by means of pulsed measurements in AlGaN and InAIN barrier devices. AlGaN barrier HEMTs have exhibited a de crease in drain current and transconductance without measurable threshold voltage change, suggesting the location of the traps in the gate-to-drain access region. On the contrary, InAIN barrier devices have showed a drain current associated with a positive shift of threshold voltage, which indicated that the traps were possibly located under the gate region. Moreover, a significant increase of the ON-resistance as well as a transconductance reduction were observed, revealing the presence of traps on the gate-drain access region. On the other hand, the assessment of devices with different geometries have demonstrated that the trapping effects are more noticeable in devices with either short gate length or the gate-to-drain distance. This can be attributed to the fact that the length and the trap density of the virtual gate are independent on the device geometry. Finally, it can be deduced that besides the final application requirements, the influence of the device geometry on the performance at high temperature, on the self-heating, as well as on the trapping effects need to be taken into account during the device design stage to achieve the optimal layout.

Server power modeling for run-time energy optimization of cloud computing facilities

As advanced Cloud services are becoming mainstream, the contribution of data centers in the overall power consumption of modern cities is growing dramatically. The average consumption of a single data center is equivalent to the energy consumption of 25.000 households. Modeling the power consumption for these infrastructures is crucial to anticipate the effects of aggressive optimization policies, but accurate and fast power modeling is a complex challenge for high-end servers not yet satisfied by analytical approaches. This work proposes an automatic method, based on Multi-Objective Particle Swarm Optimization, for the identification of power models of enterprise servers in Cloud data centers. Our approach, as opposed to previous procedures, does not only consider the workload consolidation for deriving the power model, but also incorporates other non traditional factors like the static power consumption and its dependence with temperature. Our experimental results shows that we reach slightly better models than classical approaches, but simul- taneously simplifying the power model structure and thus the numbers of sensors needed, which is very promising for a short-term energy prediction. This work, validated with real Cloud applications, broadens the possibilities to derive efficient energy saving techniques for Cloud facilities.