Investigation of AlInN barrier ISFET structures with GaN capping for pH detection

In the last decade the interest in nitride-based sensors (gas, ions...) and bio-sensors is increased. In the case of ion sensitive FET (ISFET), gate voltages induced by ions adsorbed onto the gate region modulate the source-drain currents.

Optical behaviour of cholesteric blue phases in electric fields

The optical behaviour of cholesteric mixtures of negative dielectric anisotrony under electric fields is reported. A mixture of S 311~ (31.35 %) + N 5 was employed. AC voltages (f = 1000 Hz) betweeen 0 and 150 volts were applied. Cells 23 micron thick, with internal SnO2 electrodes, were used.

Emissive Langmuir Probes in the Strong Emission Regime for the Determination of the Plasma Properties

The determination of the plasma potential Vpl of unmagnetized plasmas by using the floating potential of emissive Langmuir probes operated in the strong emission regime is investigated. The experiments evidence that, for most cases, the electron thermionic emission is orders of magnitude larger than the plasma thermal electron current. The temperature-dependent floating potentials of negatively biased Vpmenor queVpl emissive probes are in agreement with the predictions of a simple phenomenological model that considers, in addition to the plasma electrons, an ad-ditional electron group that contributes to the probe current. The latter would be constituted by a fraction of the repelled electron thermionic current, which might return back to the probe with a different energy spectrum. Its origin would be a plasma potential well formed in the plasma sheath around the probe, acting as a virtual cathode or by collisions and electron thermalization pro-cesses. These results suggest that, for probe bias voltages close to the plasma potential Vp?Vpl, two electron populations coexist, i.e., the electrons from the plasma with temperatureTeand a large group of returned thermionic electrons. These results question the theoretical possibility of measuring the electron temperature by using emissive probes biased to potentials Vp about lower equal than ?Vpl.

Variable impedance LED matrix control system for lamps in PV applications

The interest in LED lighting has been growing recently due to the high efficacy, lifelime and ruggedness that this technology offers. However the key element to guarantee those parameters with these new electronic devices is to keep under control the working temperature of the semiconductor crystal. This paper propases a LED lamp design that fulfils the requ irements of a PV lighting systems, whose main quality criteria is reliability. It uses directly as a power supply a non·stabilized constant voltage source, as batteries. An electronic control architecture is used to regulate the current applied to the LEO matri)( according to their temperature and the voltage output value of the batteries with two pulse modulation signals (PWM) signals. The first one connects and disconnects the LEOs to the power supply and the second one connects and disconnects several emitters to the electric circuit changing its overall impedance. A prototype of the LEO lamp has been implemented and tested at different temperaturas and battery voltages.

Temperature controlled light-emitting diode lamp for photovoltaic rural applications

In recent years, interest in light-emitting diode (LED) lighting has been growing because of its high efficacy, lifetime and ruggedness. This paper proposes a better adaptation of LED lamps to the technical requirements of photovoltaic lighting domestic systems, whose main quality criteria are reliability and that behave as voltage power supplies. As the key element of reliability in LED lamps is temperature, a solution is proposed for driving LED lamps using voltage sources, such as photovoltaic system batteries, with a control architecture based on pulse width modulation signal that regulates the current applied according to the LED lamp temperature. A prototype of the LED lamp has been implemented and tested to show its good performance at different temperatures and at different battery voltages.

Interleaved multi-cell isolated three-phase PWM rectifier system for aircraft applications

Recently there has been an important increase in electric equipment, as well as, electric power demand in aircrafts applications. This prompts to the necessity of efficient, reliable, and low-weight converters, especially rectifiers from 115VAC to 270VDC because these voltages are used in power distribution. In order to obtain a high efficiency, in aircraft application where the derating in semiconductors is high, normally several semiconductors are used in parallel to decrease the conduction losses. However, this is in conflict with high reliability. To match both goals of high efficiency and reliability, this work proposes an interleaved multi-cell rectifier system, employing several converter cells in parallel instead of parallel-connected semiconductors. In this work a 10kW multi-cell isolated rectifier system has been designed where each cell is composed of a buck type rectifier and a full bridge DC-DC converter. The implemented system exhibits 91% of efficiency, high power density (10kW/10kg), low THD (2.5%), and n−1 fault tolerance which complies, with military aircraft standards.

Bidirectional multiple port dc/dc transformer based on a series resonant converter

In this paper a novel bidirectional multiple port dc/dc transformer topology is presented. The novel concept for dc/dc transformer is based on the Series Resonant Converter (SRC)topology operated at its resonant frequency point. This allows for higher switching frequency to be adopted and enables high efficiency/high power density operation. The feasibility of the proposed concept is verified on a 300W, 700 kHz three port prototype with 390V input voltage and 48V and 12V output voltages. A peak overall efficiency of 93% is measured at full load. A very good load and cross regulation characteristic of the converter is observed in the whole load range, from full load to open circuit. The sensitivity analysis of the resonant capacitance is also performed showing very slight deterioration in the converter performances when a resonant capacitor is changed ±30% of its nominal value.

Analysis and validation of a multiple output series resonant converter

In this paper a novel bidirectional multiple port dc/dc transformer topology is presented. The novel concept for dc/dc transformer is based on the Series Resonant Converter (SRC) topology operated at its resonant frequency point. This allows for higher switching frequency to be adopted and enables high efficiency/high power density operation. The feasibility of the proposed concept is verified on a 300W, 700 kHz three port prototype with 390V input voltage and 48V and 12V output voltages. A peak overall efficiency of 93% is measured at full load. A very good load and cross regulation characteristic of the converter is observed in the whole load range, from full load to open circuit. The sensitivity analysis of the resonant capacitance is also performed showing very slight deterioration in the converter performances when a resonant capacitor is changed ±30% of its nominal value.

A proposed bare-tether experiment on board a sounding rocket

A mission on board a sounding rocket to carry out two bare-tether experiments is proposed: a test of orbital-motion-limited (OML) collection and the proof-of-flight of a technique to determine the (neutral) density vertical profile in the critical E-layer. Since full bias from the motional field will be small (~ 20V), corresponding to a tape 1 km long and V rocket <8 km/s, a power source with a range of supply voltages of few kV would be used. First, the negative terminal of the supply would be connected to the tape, and the positive terminal to a round, conductive boom of length 10 - 20 m; electrons collected by the boom cross the supply into the tape, where they leak out at the rate of ion impact plus secondary emission. Determination of the density profile from measurements of auroral emissions observed from the rocket, as secondaries racing down the magnetic field reach an E-layer footprint, are discussed. Next the positive terminal of the voltage supply is connected to the tape, and the negative terminal to a Hollow Cathode (HC); electrons now collected by the tape cross the supply, and are ejected at the HC. The opposite connections, with current collection operated by tape and boom, and operating on electrons and ions, and through partial switching in the supply, allow testing OML collection in almost all respects it depends on.

Two-photon photocurrent and voltage up-conversion in a quantum dot intermediate band solar cell

It has been proposed that the use of self-assembled quantum dot (QD) arrays can break the Shockley-Queisser efficiency limit by extending the absorption of solar cells into the low-energy photon range while preserving their output voltage. This would be possible if the infrared photons are absorbed in the two sub-bandgap QD transitions simultaneously and the energy of two photons is added up to produce one single electron-hole pair, as described by the intermediate band model. Here, we present an InAs/Al 0.25Ga 0.75As QD solar cell that exhibits such electrical up-conversion of low-energy photons. When the device is monochromatically illuminated with 1.32 eV photons, open-circuit voltages as high as 1.58 V are measured (for a total gap of 1.8 eV). Moreover, the photocurrent produced by illumination with photons exciting the valence band to intermediate band (VB-IB) and the intermediate band to conduction band (IB-CB) transitions can be both spectrally resolved. The first corresponds to the QD inter-band transition and is observable for photons of energy mayor que 1 eV, and the later corresponds to the QD intra-band transition and peaks around 0.5 eV. The voltage up-conversion process reported here for the first time is the key to the use of the low-energy end of the solar spectrum to increase the conversion efficiency, and not only the photocurrent, of single-junction photovoltaic devices. In spite of the low absorption threshold measured in our devices - 0.25 eV - we report open-circuit voltages at room temperature as high as 1.12 V under concentrated broadband illumination.

Instabilities in hybrid liquid crystal optical bistable devices

In this paper we report some of the experimental results that can be obtained in the field of hybrid optical bistable devices when liquid crystals are employed as non linear materials. The advantages with respect to other materials are the very low voltages and power needed, compatibles with I.C.'s levels.

A novel high-sensitivity, low-power, liquid crystal temperature sensor

A novel temperature sensor based on nematic liquid crystal permittivity as a sensing magnitude, is presented. This sensor consists of a specific micrometric structure that gives considerable advantages from other previous related liquid crystal (LC) sensors. The analytical study reveals that permittivity change with temperature is introduced in a hyperbolic cosine function, increasing the sensitivity term considerably. The experimental data has been obtained for ranges from −6 °C to 100 °C. Despite this, following the LC datasheet, theoretical ranges from −40 °C to 109 °C could be achieved. These results have revealed maximum sensitivities of 33 mVrms/°C for certain temperature ranges; three times more than of most silicon temperature sensors. As it was predicted by the analytical study, the micrometric size of the proposed structure produces a high output voltage. Moreover the voltage’s sensitivity to temperature response can be controlled by the applied voltage. This response allows temperature measurements to be carried out without any amplification or conditioning circuitry, with very low power consumption.

Modal liquid crystal microaxicon array

A novel tunable liquid crystal microaxicon array is proposed and experimentally demonstrated. The proposed structure is capable of generating tunable axicons (thousands of elements) of micrometric size, with simple control (four control voltages) and low voltage, and is totally reconfigurable. Depending on the applied voltages, control over the diameter, as well as the effective wedge angle, can be achieved. Controls over the diameter ranging from 107 to 77 μm have been demonstrated. In addition, a control over the phase profile tunability, from 12π to 24π radians, has been demonstrated. This result modifies the effective cone angle. The diameter tunability, as well the effective cone angle, results in a control over the nondiffractive Bessel beam distance. The RMS wavefront deviation from the ideal axicon is only λ∕3. The proposed device has several advantages over the existing microaxicon arrays, including being simple having a low cost. The device could contribute to developing new applications and to reducing the fabrication costs of current devices.

Design and Simulation of Deep Nanometer SRAM Cells under Energy, Mismatch, and Radiation Constraints

La fiabilidad está pasando a ser el principal problema de los circuitos integrados según la tecnología desciende por debajo de los 22nm. Pequeñas imperfecciones en la fabricación de los dispositivos dan lugar ahora a importantes diferencias aleatorias en sus características eléctricas, que han de ser tenidas en cuenta durante la fase de diseño. Los nuevos procesos y materiales requeridos para la fabricación de dispositivos de dimensiones tan reducidas están dando lugar a diferentes efectos que resultan finalmente en un incremento del consumo estático, o una mayor vulnerabilidad frente a radiación. Las memorias SRAM son ya la parte más vulnerable de un sistema electrónico, no solo por representar más de la mitad del área de los SoCs y microprocesadores actuales, sino también porque las variaciones de proceso les afectan de forma crítica, donde el fallo de una única célula afecta a la memoria entera. Esta tesis aborda los diferentes retos que presenta el diseño de memorias SRAM en las tecnologías más pequeñas. En un escenario de aumento de la variabilidad, se consideran problemas como el consumo de energía, el diseño teniendo en cuenta efectos de la tecnología a bajo nivel o el endurecimiento frente a radiación. En primer lugar, dado el aumento de la variabilidad de los dispositivos pertenecientes a los nodos tecnológicos más pequeños, así como a la aparición de nuevas fuentes de variabilidad por la inclusión de nuevos dispositivos y la reducción de sus dimensiones, la precisión del modelado de dicha variabilidad es crucial. Se propone en la tesis extender el método de inyectores, que modela la variabilidad a nivel de circuito, abstrayendo sus causas físicas, añadiendo dos nuevas fuentes para modelar la pendiente sub-umbral y el DIBL, de creciente importancia en la tecnología FinFET. Los dos nuevos inyectores propuestos incrementan la exactitud de figuras de mérito a diferentes niveles de abstracción del diseño electrónico: a nivel de transistor, de puerta y de circuito. El error cuadrático medio al simular métricas de estabilidad y prestaciones de células SRAM se reduce un mínimo de 1,5 veces y hasta un máximo de 7,5 a la vez que la estimación de la probabilidad de fallo se mejora en varios ordenes de magnitud. El diseño para bajo consumo es una de las principales aplicaciones actuales dada la creciente importancia de los dispositivos móviles dependientes de baterías. Es igualmente necesario debido a las importantes densidades de potencia en los sistemas actuales, con el fin de reducir su disipación térmica y sus consecuencias en cuanto al envejecimiento. El método tradicional de reducir la tensión de alimentación para reducir el consumo es problemático en el caso de las memorias SRAM dado el creciente impacto de la variabilidad a bajas tensiones. Se propone el diseño de una célula que usa valores negativos en la bit-line para reducir los fallos de escritura según se reduce la tensión de alimentación principal. A pesar de usar una segunda fuente de alimentación para la tensión negativa en la bit-line, el diseño propuesto consigue reducir el consumo hasta en un 20 % comparado con una célula convencional. Una nueva métrica, el hold trip point se ha propuesto para prevenir nuevos tipos de fallo debidos al uso de tensiones negativas, así como un método alternativo para estimar la velocidad de lectura, reduciendo el número de simulaciones necesarias. Según continúa la reducción del tamaño de los dispositivos electrónicos, se incluyen nuevos mecanismos que permiten facilitar el proceso de fabricación, o alcanzar las prestaciones requeridas para cada nueva generación tecnológica. Se puede citar como ejemplo el estrés compresivo o extensivo aplicado a los fins en tecnologías FinFET, que altera la movilidad de los transistores fabricados a partir de dichos fins. Los efectos de estos mecanismos dependen mucho del layout, la posición de unos transistores afecta a los transistores colindantes y pudiendo ser el efecto diferente en diferentes tipos de transistores. Se propone el uso de una célula SRAM complementaria que utiliza dispositivos pMOS en los transistores de paso, así reduciendo la longitud de los fins de los transistores nMOS y alargando los de los pMOS, extendiéndolos a las células vecinas y hasta los límites de la matriz de células. Considerando los efectos del STI y estresores de SiGe, el diseño propuesto mejora los dos tipos de transistores, mejorando las prestaciones de la célula SRAM complementaria en más de un 10% para una misma probabilidad de fallo y un mismo consumo estático, sin que se requiera aumentar el área. Finalmente, la radiación ha sido un problema recurrente en la electrónica para aplicaciones espaciales, pero la reducción de las corrientes y tensiones de los dispositivos actuales los está volviendo vulnerables al ruido generado por radiación, incluso a nivel de suelo. Pese a que tecnologías como SOI o FinFET reducen la cantidad de energía colectada por el circuito durante el impacto de una partícula, las importantes variaciones de proceso en los nodos más pequeños va a afectar su inmunidad frente a la radiación. Se demuestra que los errores inducidos por radiación pueden aumentar hasta en un 40 % en el nodo de 7nm cuando se consideran las variaciones de proceso, comparado con el caso nominal. Este incremento es de una magnitud mayor que la mejora obtenida mediante el diseño de células de memoria específicamente endurecidas frente a radiación, sugiriendo que la reducción de la variabilidad representaría una mayor mejora. ABSTRACT Reliability is becoming the main concern on integrated circuit as the technology goes beyond 22nm. Small imperfections in the device manufacturing result now in important random differences of the devices at electrical level which must be dealt with during the design. New processes and materials, required to allow the fabrication of the extremely short devices, are making new effects appear resulting ultimately on increased static power consumption, or higher vulnerability to radiation SRAMs have become the most vulnerable part of electronic systems, not only they account for more than half of the chip area of nowadays SoCs and microprocessors, but they are critical as soon as different variation sources are regarded, with failures in a single cell making the whole memory fail. This thesis addresses the different challenges that SRAM design has in the smallest technologies. In a common scenario of increasing variability, issues like energy consumption, design aware of the technology and radiation hardening are considered. First, given the increasing magnitude of device variability in the smallest nodes, as well as new sources of variability appearing as a consequence of new devices and shortened lengths, an accurate modeling of the variability is crucial. We propose to extend the injectors method that models variability at circuit level, abstracting its physical sources, to better model sub-threshold slope and drain induced barrier lowering that are gaining importance in FinFET technology. The two new proposed injectors bring an increased accuracy of figures of merit at different abstraction levels of electronic design, at transistor, gate and circuit levels. The mean square error estimating performance and stability metrics of SRAM cells is reduced by at least 1.5 and up to 7.5 while the yield estimation is improved by orders of magnitude. Low power design is a major constraint given the high-growing market of mobile devices that run on battery. It is also relevant because of the increased power densities of nowadays systems, in order to reduce the thermal dissipation and its impact on aging. The traditional approach of reducing the voltage to lower the energy consumption if challenging in the case of SRAMs given the increased impact of process variations at low voltage supplies. We propose a cell design that makes use of negative bit-line write-assist to overcome write failures as the main supply voltage is lowered. Despite using a second power source for the negative bit-line, the design achieves an energy reduction up to 20% compared to a conventional cell. A new metric, the hold trip point has been introduced to deal with new sources of failures to cells using a negative bit-line voltage, as well as an alternative method to estimate cell speed, requiring less simulations. With the continuous reduction of device sizes, new mechanisms need to be included to ease the fabrication process and to meet the performance targets of the successive nodes. As example we can consider the compressive or tensile strains included in FinFET technology, that alter the mobility of the transistors made out of the concerned fins. The effects of these mechanisms are very dependent on the layout, with transistor being affected by their neighbors, and different types of transistors being affected in a different way. We propose to use complementary SRAM cells with pMOS pass-gates in order to reduce the fin length of nMOS devices and achieve long uncut fins for the pMOS devices when the cell is included in its corresponding array. Once Shallow Trench isolation and SiGe stressors are considered the proposed design improves both kinds of transistor, boosting the performance of complementary SRAM cells by more than 10% for a same failure probability and static power consumption, with no area overhead. While radiation has been a traditional concern in space electronics, the small currents and voltages used in the latest nodes are making them more vulnerable to radiation-induced transient noise, even at ground level. Even if SOI or FinFET technologies reduce the amount of energy transferred from the striking particle to the circuit, the important process variation that the smallest nodes will present will affect their radiation hardening capabilities. We demonstrate that process variations can increase the radiation-induced error rate by up to 40% in the 7nm node compared to the nominal case. This increase is higher than the improvement achieved by radiation-hardened cells suggesting that the reduction of process variations would bring a higher improvement.

A voltage disturbances prototype for testing electrical generators connected to microgrids

The search for new energy models arises as a necessity to have a sustainable power supply. The inclusion of distributed generation sources (DG) allows to reduce the cost of facilities, increase the security of the grid or alleviate problems of congestion through the redistribution of power flows. In remote microgrids it is needed in a particular way a safe and reliable supply, which can cover the demand for a low cost; due to this, distributed generation is an alternative that is being widely introduced in these grids. But the remote microgrids are especially weak grids because of their small size, low voltage level, reduced network mesh and distribution lines with a high ratio R/X. This ratio affects the coupling between grid voltages and phase shifts, and stability becomes an issue of greater importance than in interconnected systems. To ensure the appropriate behavior of generation sources inserted in remote microgrids -and, in general, any electrical equipment-, it is essential to have devices for testing and certification. These devices must, not only faithfully reproduce disturbances occurring in remote microgrids, but also to behave against the equipment under test (EUT) as a real weak grid. This also makes the device commercially competitive. To meet these objectives and based on the aforementioned, it has been designed, built and tested a voltage disturbances generator, in order to provide a simple, versatile, full and easily scalable device to manufacturers and laboratories in the sector.