Analysis and design of multirate synchronous sampling schemes for sparse multiband signals

We consider the problem of developing efficient sampling schemes for multiband sparse signals. Previous results on multicoset sampling implementations that lead to universal sampling patterns (which guarantee perfect reconstruction), are based on a set of appropriate interleaved analog to digital converters, all of them operating at the same sampling frequency. In this paper we propose an alternative multirate synchronous implementation of multicoset codes, that is, all the analog to digital converters in the sampling scheme operate at different sampling frequencies, without need of introducing any delay. The interleaving is achieved through the usage of different rates, whose sum is significantly lower than the Nyquist rate of the multiband signal. To obtain universal patterns the sampling matrix is formulated and analyzed. Appropriate choices of the parameters, that is the block length and the sampling rates, are also proposed.

A Monitoring Infrastructure for FPGA Self-Awareness and Dynamic Adaptation

Variabilities associated with CMOS evolution affect the yield and performance of current digital designs. FPGAs, which are widely used for fast prototyping and implementation of digital circuits, also suffer from these issues. Proactive approaches start to appear to achieve self-awareness and dynamic adaptation of these devices. To support these techniques we propose the employment of a multi-purpose sensor network. This infrastructure, through adequate use of configuration and automation tools, is able to obtain relevant data along the life cycle of an FPGA. This is realised at a very reduced cost, not only in terms of area or other limited resources, but also regarding the design effort required to define and deploy the measuring infrastructure. Our proposal has been validated by measuring inter-die and intra-die variability in different FPGA families.

Synchronous Buck converter with Output Impedance Correction Circuit

This work is related to the improvement of the output impedance of the Buck converter by means of introducing an additional power path that virtually increases the output capacitance during transients. It is well known that in VRM applications, with wide load steps, voltage overshoots and undershoots may lead to undesired performance of the load. To solve this problem, high-bandwidth high-switching frequency power converters can be applied to reduce the transient time or a big output capacitor can be applied to reduce the output impedance. The first solution can degrade the efficiency by increasing switching losses of the MOSFETS, and the second solution is penalizing the cost and size of the output filter. The Output Impedance Correction Circuit (OICC), as presented here, is used to inject or extract a current n-1 times larger than the output capacitor current, thus virtually increasing n times the value of the output capacitance during the transients. This feature allows the usage of a low frequency Buck converter with smaller capacitor but satisfying the dynamic requirements.

Loss model for a high frequency and low load DC/DC synchronous buck converter

This work presents a behavioral-analytical hybrid loss model for a buck converter. The model has been designed for a wide operating frequency range up to 4MHz and a low power range (below 20W). It is focused on the switching losses obtained in the power MOSFETs. Main advantages of the model are the fast calculation time and a good accuracy. It has been validated by simulation and experimentally with one Ga, power transistor and two Si MOSFETs. Results show good agreement between measurements and the model.

Synchronizing chaotic optically-programmable digital circuits

In this paper an approach to the synchronization of chaotic circuits has been reported. It is based on an optically programmable logic cell and the signals involved are fully digital. It is based on the reception of the same input signal on sender and receiver and from this approach, with a posterior correlation between both outputs, an identical chaotic output is obtained in both systems. No conversion from analog to digital signals is needed. The model here presented is based on a computer simulation.

First order mem-circuits: modeling, nonlinear oscillations and bifurcations

This paper presents a theoretical framework intended to accommodate circuit devices described by characteristics involving more than two fundamental variables. This framework is motivated by the recent appearance of a variety of so-called mem-devices in circuit theory, and makes it possible to model the coexistence of memory effects of different nature in a single device. With a compact formalism, this setting accounts for classical devices and also for circuit elements which do not admit a two-variable description. Fully nonlinear characteristics are allowed for all devices, driving the analysis beyond the framework of Chua and Di Ventra We classify these fully nonlinear circuit elements in terms of the variables involved in their constitutive relations and the notions of the differential- and the state-order of a device. We extend the notion of a topologically degenerate configuration to this broader context, and characterize the differential-algebraic index of nodal models of such circuits. Additionally, we explore certain dynamical features of mem-circuits involving manifolds of non-isolated equilibria. Related bifurcation phenomena are explored for a family of nonlinear oscillators based on mem-devices.

Hybrid analysis of nonlinear circuits: DAE models with indices zero and one

We extend in this paper some previous results concerning the differential-algebraic index of hybrid models of electrical and electronic circuits. Specifically, we present a comprehensive index characterization which holds without passivity requirements, in contrast to previous approaches, and which applies to nonlinear circuits composed of uncoupled, one-port devices. The index conditions, which are stated in terms of the forest structure of certain digraph minors, do not depend on the specific tree chosen in the formulation of the hybrid equations. Additionally, we show how to include memristors in hybrid circuit models; in this direction, we extend the index analysis to circuits including active memristors, which have been recently used in the design of nonlinear oscillators and chaotic circuits. We also discuss the extension of these results to circuits with controlled sources, making our framework of interest in the analysis of circuits with transistors, amplifiers, and other multiterminal devices.

A 0.0016 mm(2) 0.64 nJ leakage-based CMOS temperature sensor

This paper presents a CMOS temperature sensor based on the thermal dependencies of the leakage currents targeting the 65 nm node. To compensate for the effect of process fluctuations, the proposed sensor realizes the ratio of two measures of the time it takes a capacitor to discharge through a transistor in the subthreshold regime. Furthermore, a novel charging mechanism for the capacitor is proposed to further increase the robustness against fabrication variability. The sensor, including digitization and interfacing, occupies 0.0016 mm2 and has an energy consumption of 47.7–633 pJ per sample. The resolution of the sensor is 0.28 °C, and the 3σ inaccuracy over the range 40–110 °C is 1.17 °C.

Receptores homodinos a 300 GHz basados en tecnología CMOS

Using CMOS transistors for terahertz detection is currently a disruptive technology that offers the direct integration of a terahertz detector with video preamplifiers. The detectors are based on the resistive mixer concept and its performance mainly depends on the following parameters: type of antenna, electrical parameters (gate to drain capacitor and channel length of the CMOS device) and foundry. Two different 300 GHz detectors are discussed: a single transistor detector with a broadband antenna and a differential pair driven by a resonant patch antenna.

AVR adjustment of Synchronous Generators in Weak Grids under Faulty Conditions.

In weak grids, an important problem with voltage stability and protections coordination of power plants exists. This problem appears because all the generation groups are connected to the same bus bar. As a result, if a fault occurs in any of the generation groups, or in the bus bar that connect them, the system voltage will have large oscillations. Hence, in weak grids the correct adjustment of AVR (Automatic Voltage Regulator) is critical. In this work an experimental study of differents AVR adjustments against fault in weak grids is described.

Evaluation of the Grounding Circuit Measurements for Stator Ground-Fault Location of Synchronous Generators

Locating stator-winding ground faults accurately is a very difficult task. In this paper the grounding circuit measurements are evaluated in order to obtain information about the stator ground-fault location in synchronous generators. In power generators grounded through a high impedance, the relation between the neutral voltage and the phase voltage provide a first estimation of the fault location. The location error by using this ratio depends on the fault resistance and the value of the capacitance to ground of the stator winding. However, the error added by ignoring the value of the fault resistance is the most relevant term. This location estimation and the location error have been evaluated through the data of a real synchronous machine.

Consideration of Multi-Phase Criterion in the Differential Protection Algorithm for High-Impedance Grounded Synchronous Generators

The generator differential protection is one of the most important electrical protections of synchronous generator stator windings. Its operation principle is based on the comparison of the input current and output current at each phase winding. Unwanted trip commands are usually caused by CT saturation, wrong CT selection, or the fact that they may come from different manufacturers. In generators grounded through high impedance, only phase-to-phase or three-phase faults can be detected by the differential protection. This kind of fault causes differential current to flow in, at least, two phases of the winding. Several cases of unwanted trip commands caused by the appearance of differential current in only one phase of the generator have been reported. In this paper multi-phase criterion is proposed for generator differential protection algorithm when applied to high impedance grounded generators.

Improvement of the Dynamic Performance of a Multiphase Current Controlled Buck Converter using an Auxiliary Synchronous Buck Converter as an Additional Energy Path

This work is related to the output impedance improvement of a Multiphase Buck converter with Peak Current Mode Control (PCMC) by means of introducing an additional power path that virtually increases the output capacitance during transients. Various solutions that can be employed to improve the dynamic behavior of the converter system exist, but nearly all solutions are developed for a Single Phase Buck converter with Voltage Mode Control (VMC), while in the VRM applications, due to the high currents, the system is usually implemented as a Multiphase Buck Converter with Current Mode Control. The additional energy path, as presented here, is introduced with the Output Impedance Correction Circuit (OICC) based on the Controlled Current Source (CCS). The OICC is used to inject or extract a current n-1 times larger than the output capacitor current, thus virtually increasing n times the value of the output capacitance during the transients. Furthermore, this work extends the OICC concept to a Multiphase Buck Converter system while comparing proposed solution with the system that has n times bigger output capacitor. In addition, the OICC is implemented as a Synchronous Buck Converter with PCMC, thus reducing its influence on the system efficiency.

300 GHz CMOS video detection using broadband and active planar antennas

Using CMOS transistors for terahertz detection is currently a disruptive technology that offers the direct integration of a terahertz detector with video preamplifiers. The detectors are based on the resistive mixer concept and performance mainly depends on the following parameters: type of antenna, electrical parameters (gate to drain capacitor and channel length of the CMOS device) and foundry. Two different 300 GHz detectors are discussed: a single transistor detector with a broadband antenna and a differential pair driven by a resonant patch antenna.

Ripple cancellation technique applied to a synchronous buck converter to achieve very high bandwidth and very high efficiency envelope amplifier

This work presents a single stage converter for a high bandwidth and a high efficiency envelope amplifier. The current ripple cancellation technique is applied to a synchronous buck converter to cancel the output current ripple and to decrease the switching frequency without a reduction in the large signal bandwidth. The converter is modeled and the new design with ripple cancellation circuit is detailed. The advantages of the proposed design are presented and validated experimentally. The transfer function of the output filter of the buck converter with ripple cancellation circuit has been modeled and compared to measurements, showing a good correspondence. Experimental validation is provided at 4MHz of switching frequency for DC and variable output voltage for a sinusoidal and a 64QAM signal. Additional experimental validation of the efficiency improvement is provided, compared to the equivalent design (same bandwidth and output voltage ripple) of the conventional buck converter.