Advanced Nuclear Energy Systems: Heat Transfer Issues and Trends

Almost 450 nuclear power plants are currently operating throughout the world and supplying about 17% of the world’s electricity. These plants perform safely, reliably, and have no free-release of byproducts to the environment. Given the current rate of growth in electricity demand and the ever growing concerns for the environment, the US consumer will favor energy sources that can satisfy the need for electricity and other energy-intensive products (1) on a sustainable basis with minimal environmental impact, (2) with enhanced reliability and safety and (3) competitive economics. Given that advances are made to fully apply the potential benefits of nuclear energy systems, the next generation of nuclear systems can provide a vital part of a long-term, diversified energy supply. The Department of Energy has begun research on such a new generation of nuclear energy systems that can be made available to the market by 2030 or earlier, and that can offer significant advances toward these challenging goals [1]. These future nuclear power systems will require advances in materials, reactor physics as well as heat transfer to realize their full potential. In this paper, a summary of these advanced nuclear power systems is presented along with a short synopsis of the important heat transfer issues. Given the nature of research and the dynamics of these conceptual designs, key aspects of the physics will be provided, with details left for the presentation.

Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic

The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. In this work we present a number of new CMOS logic families, Charge Recovery Logic (CRL) as well as the much improved Split-Level Charge Recovery Logic (SCRL), within which the transfer of charge between the nodes occurs quasistatically. Operating quasistatically, these logic families have an energy dissipation that drops linearly with operating frequency, i.e., their power consumption drops quadratically with operating frequency as opposed to the linear drop of conventional CMOS. The circuit techniques in these new families rely on constructing an explicitly reversible pipelined logic gate, where the information necessary to recover the energy used to compute a value is provided by computing its logical inverse. Information necessary to uncompute the inverse is available from the subsequent inverse logic stage. We demonstrate the low energy operation of SCRL by presenting the results from the testing of the first fully quasistatic 8 x 8 multiplier chip (SCRL-1) employing SCRL circuit techniques.

Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.