Growth and Characterization of LiCoO₂ Thin Films for Microbatteries

LiCoO₂thin films have been grown by pulsed laser deposition on stainless steel and SiO₂/Si substrates. The film deposited at 600°C in an oxygen partial pressure of 100mTorr shows an excellent crystallinity, stoichiometry and no impurity phase present. Microstructure and surface morphology of thin films were examined using a scanning electron microscope. The electrochemical properties of the thin films were studied with cyclic voltammetry and galvanostatic charge-discharge techniques in the potential range 3.0-4.2 V. The initial discharge capacity of the LiCoO2 thin films deposited on the stainless steel and SiO₂/Si substrates reached 23 and 27 µAh/cm², respectively.

High Indium Concentration InGaN/GaN Grown on Sapphire Substrate by MOCVD

The InGaN system provides the opportunity to fabricate light emitting devices over the whole visible and ultraviolet spectrum due to band-gap energies E[subscript g] varying between 3.42 eV for GaN and 1.89 eV for InN. However, high In content in InGaN layers will result in a significant degradation of the crystalline quality of the epitaxial layers. In addition, unlike other III-V compound semiconductors, the ratio of gallium to indium incorporated in InGaN is in general not a simple function of the metal atomic flux ratio, f[subscript Ga]/f[subscript In]. Instead, In incorporation is complicated by the tendency of gallium to incorporate preferentially and excess In to form metallic droplets on the growth surface. This phenomenon can definitely affect the In distribution in the InGaN system. Scanning electron microscopy, room temperature photoluminescence, and X-ray diffraction techniques have been used to characterize InGaN layer grown on InN and InGaN buffers. The growth was done on c-plane sapphire by MOCVD. Results showed that green emission was obtained which indicates a relatively high In incorporation.

Preliminary Characterisation of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits

Three dimensional (3-D) integrated circuits can be fabricated by bonding previously processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnects test structures were created by thermocompression bonding and the bond toughness was measured using the four-point test. The effects of bonding temperature, physical bonding and failure mechanisms were investigated. The surface effects on copper surface due to pre-bond clean (with glacial acetic acid) were also looked into. A maximum average bond toughness of approximately 35 J/m² was obtained bonding temperature 300 C.

A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing

The present success in the manufacture of multi-layer interconnects in ultra-large-scale integration is largely due to the acceptable planarization capabilities of the chemical-mechanical polishing (CMP) process. In the past decade, copper has emerged as the preferred interconnect material. The greatest challenge in Cu CMP at present is the control of wafer surface non-uniformity at various scales. As the size of a wafer has increased to 300 mm, the wafer-level non-uniformity has assumed critical importance. Moreover, the pattern geometry in each die has become quite complex due to a wide range of feature sizes and multi-level structures. Therefore, it is important to develop a non-uniformity model that integrates wafer-, die- and feature-level variations into a unified, multi-scale dielectric erosion and Cu dishing model. In this paper, a systematic way of characterizing and modeling dishing in the single-step Cu CMP process is presented. The possible causes of dishing at each scale are identified in terms of several geometric and process parameters. The feature-scale pressure calculation based on the step-height at each polishing stage is introduced. The dishing model is based on pad elastic deformation and the evolving pattern geometry, and is integrated with the wafer- and die-level variations. Experimental and analytical means of determining the model parameters are outlined and the model is validated by polishing experiments on patterned wafers. Finally, practical approaches for minimizing Cu dishing are suggested.

A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing

The present success in the manufacture of multi-layer interconnects in ultra-large-scale integration is largely due to the acceptable planarization capabilities of the chemical-mechanical polishing (CMP) process. In the past decade, copper has emerged as the preferred interconnect material. The greatest challenge in Cu CMP at present is the control of wafer surface non-uniformity at various scales. As the size of a wafer has increased to 300 mm, the wafer-level non-uniformity has assumed critical importance. Moreover, the pattern geometry in each die has become quite complex due to a wide range of feature sizes and multi-level structures. Therefore, it is important to develop a non-uniformity model that integrates wafer-, die- and feature-level variations into a unified, multi-scale dielectric erosion and Cu dishing model. In this paper, a systematic way of characterizing and modeling dishing in the single-step Cu CMP process is presented. The possible causes of dishing at each scale are identified in terms of several geometric and process parameters. The feature-scale pressure calculation based on the step-height at each polishing stage is introduced. The dishing model is based on pad elastic deformation and the evolving pattern geometry, and is integrated with the wafer- and die-level variations. Experimental and analytical means of determining the model parameters are outlined and the model is validated by polishing experiments on patterned wafers. Finally, practical approaches for minimizing Cu dishing are suggested.

Corner Flows in Free Liquid Films

A lubrication-flow model for a free film in a corner is presented. The model, written in the hyperbolic coordinate system ξ = x² – y², η = 2xy, applies to films that are thin in the η direction. The lubrication approximation yields two coupled evolution equations for the film thickness and the velocity field which, to lowest order, describes plug flow in the hyperbolic coordinates. A free film in a corner evolving under surface tension and gravity is investigated. The rate of thinning of a free film is compared to that of a film evolving over a solid substrate. Viscous shear and normal stresses are both captured in the model and are computed for the entire flow domain. It is shown that normal stress dominates over shear stress in the far field, while shear stress dominates close to the corner.