3 resultados para Capability Hierarchy
em Massachusetts Institute of Technology
Resumo:
This volume of the final report documents the technical work performed from December 1998 through December 2002 under Cooperative Agreement F33615-97-2-5153 executed between the U.S. Air Force, Air Force Research Laboratory, Materials and Manufacturing Directorate, Manufacturing Technology Division (AFRL/MLM) and the McDonnell Douglas Corporation, a wholly-owned subsidiary of The Boeing Company. The work was accomplished by The Boeing Company, Phantom Works, Huntington Beach, St. Louis, and Seattle; Ford Motor Company; Integral Inc.; Sloan School of Management in the Massachusetts Institute of Technology; Pratt & Whitney; and Central State University in Xenia, Ohio and in association with Raytheon Corporation. The LeanTEC program manager for AFRL is John Crabill of AFRL / MLMP and The Boeing Company program manager is Ed Shroyer of Boeing Phantom Works in Huntington Beach, CA. Financial performance under this contract is documented in the Financial Volume of the final report.
Resumo:
The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.
Resumo:
Lean Transition of Emerging Industrial Capability (LeanTEC) program was a cooperative agreement between the Boeing Company and AFRL conducted from January 1998 to January 2002. The results of this program are documented in the Manual for Effective Technology Transition Processes included as an attachment to this report. This manual provides processes, procedures, and tools for greatly improving technology transition in the aerospace industry. Methodology for the implementation of these improvements is given along with methods for customizing the various processes, procedures, and tools for a given company or business unit. The indicated methodology was tested by the LeanTEC team and results are documented in the report.