A new single-phase frequency adaptive Phase-Locked Loop (PLL) for harmonic measurement

The paper presents an improved Phase-Locked Loop (PLL) for measuring the fundamental frequency and selective harmonic content of a distorted signal. This information can be used by grid interfaced devices and harmonic compensators. The single-phase structure is based on the Synchronous Reference Frame (SRF) PLL. The proposed PLL needs only a limited number of harmonic stages by incorporating Moving Average Filters (MAF) for eliminating the undesired harmonic content at each stage. The frequency dependency of MAF in effective filtering of undesired harmonics is also dealt with by a proposed method for adaptation to frequency variations of input signal. The method is suitable for high sampling rates and a wide frequency measurement range. Furthermore, an extended model of this structure is proposed which includes the response to both the frequency and phase angle variations. The proposed algorithm is simulated and verified using Hardware-in-the-Loop (HIL) testing.

A Resonant Integrator Based PLL and AC Current Controller for Single Phase Grid Connected PWM-VSI

Grid connected PWM-VSIs are being increasingly used for applications such as Distributed Generation (DG), power quality, UPS etc. Appropriate control strategies for grid synchronisation and line current regulation are required to establish such a grid interconnection and power transfer. Control of three phase VSIs is widely reported in iterature. Conventionally, dq control in Synchronous Reference Frame(SRF) is employed for both PLL and line current control where PI-controllers are used to track the DC references. Single phase systems do not have defined direct (d) and quadrature (q) axis components that are required for SRF transformation. Thus, references are AC in nature and hence usage of PI controllers cannot yield zero steady state errors. Resonant controllers have the ability to track AC references accurately. In this work, a resonant controller based single phase PLL and current control technique are being employed for tracking grid frequency and the AC current reference respectively. A single phase full bridge converter is being operated as a STATCOM for performance evaluation of the control scheme.

Analysis of Bandwidth-Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions

Phase-locked loops (PLLs) are necessary in applications which require grid synchronization. Presence of unbalance or harmonics in the grid voltage creates errors in the estimated frequency and angle of a PLL. The error in estimated angle has the effect of distorting the unit vectors generated by the PLL. In this paper, analytical expressions are derived which determine the error in the phase angle estimated by a PLL when there is unbalance and harmonics in the grid voltage. By using the derived expressions, the total harmonic distortion (THD) and the fundamental phase error of the unit vectors can be determined for a given PLL topology and a given level of unbalance and distortion in the grid voltage. The accuracy of the results obtained from the analytical expressions is validated with the simulation and experimental results for synchronous reference frame PLL (SRF-PLL). Based on these expressions, a new tuning method for the SRF-PLL is proposed which quantifies the tradeoff between the unit vector THD and the bandwidth of the SRF-PLL. Using this method, the exact value of the bandwidth of the SRF-PLL can be obtained for a given worst case grid voltage unbalance and distortion to have an acceptable level of unit vector THD. The tuning method for SRF-PLL is also validated experimentally.

Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13-mu m CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

A Novel Design Method for SOGI-PLL for Minimum Settling Time and Low Unit Vector Distortion

Phase-locked loops (PLLs) are necessary in grid connected systems to obtain information about the frequency, amplitude and phase of the grid voltage. In stationary reference frame control, the unit vectors of PLLs are used for reference generation. It is important that the PLL performance is not affected significantly when grid voltage undergoes amplitude and frequency variations. In this paper, a novel design for the popular single-phase PLL topology, namely the second-order generalized integrator (SOGI) based PLL is proposed which achieves minimum settling time during grid voltage amplitude and frequency variations. The proposed design achieves a settling time of less than 27.7 ms. This design also ensures that the unit vectors generated by this PLL have a steady state THD of less than 1% during frequency variations of the grid voltage. The design of the SOGI-PLL based on the theoretical analysis is validated by experimental results.

An Accurate and Fast Behavioral Model for PLL Frequency Synthesizer Phase Noise/Spurs Prediction

This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.

A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.

A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction

This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixed-signal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input Was implemented in a 0.18μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3μs,and the phase noise is -108 dBc/Hz@1MHz.The reference spur is -52 dBc.

Construction of hollow DNA/PLL microcapsule as a dual carrier for controlled delivery of DNA and drug

DNA/poly-L-lysine (PLL) capsules were constructed through a layer-by-layer (LbL) self-assembly of DNA and PLL on CaCO3 microparticles, and then used as dual carriers for DNA and drug after dissolution of carbonate cores. The permeability of DNA/PLL microcapsules was investigated with fluorescence probes with different molecular weights by confocal microscopy. The result revealed that the fluorescence probes were able to penetrate the capsule walls even its molecular weight up to 150 kDa. The resultant capsules were used to load drug model molecules-fluorescein isothiocyanate (FITC)-dextran (4 kDa) via spontaneous deposition mechanism.

Hollow DNA/PLL microcapsules with tunable degradation property as efficient dual drug delivery vehicles by alpha-chymotrypsin degradation

Hollow deoxyribonucleic acid (DNA)/poly-L-lysine (PLL) capsules were successfully fabricated through a layer-by-layer (LbL) self-assembly of DNA and PLL on porous CaCO3 microparticles, followed by removal of templates with ethylenediamine tetraacetic acid disodium salt (EDTA). The enzymatic degradation of the capsules in the presence of alpha-chymotrypsin was explored. The higher the enzyme concentration, the higher is the degradation rate of hollow capsules. in addition, glutaric dialdehyde (GA) cross-linking was found to be another way to manipulate degradation rate of hollow capsules.

Statistical properties of first-order bang-bang Pll with nonzero loop delay

A method to solve the stationary state probability is presented for the first-order bang-bang phase-locked loop (BBPLL) with nonzero loop delay. This is based on a delayed Markov chain model and a state How diagram for tracing the state history due to the loop delay. As a result, an eigenequation is obtained, and its closed form solutions are derived for some cases. After obtaining the state probability, statistical characteristics such as mean gain of the binary phase detector and timing error variance are calculated and demonstrated.

A pll based frequency synthesizer in 0.13 um sige bicmos for mb-ofdm uwb systems

With the growing demand for high-speed and high-quality short-range communication, multi-band orthogonal frequency division multiplexing ultra-wide band (MB-OFDM UWB) systems have recently garnered considerable interest in industry and in academia. To achieve a low-cost solution, highly integrated transceivers with small die area and minimum power consumption are required. The key building block of the transceiver is the frequency synthesizer. A frequency synthesizer comprised of two PLLs and one multiplexer is presented in this thesis. Ring oscillators are adopted for PLL implementation in order to drastically reduce the die area of the frequency synthesizer. The poor spectral purity appearing in the frequency synthesizers involving mixers is greatly improved in this design. Based on the specifications derived from application standards, a design methodology is presented to obtain the parameters of building blocks. As well, the simulation results are provided to verify the performance of proposed design.

PLL with secondary loop control for self tracking antennas

This paper shows a simple, yet highly effective, tracking phase locked loop circuit which has applications for self steered antenna arrays. The tracking PLL has been demonstrated to accurately phase track signal levels as low as -120 dBm, making it suitable for applications such as SATCOM ground terminals. The implementation is simple requiring a low Q voltage controlled oscillator, a downconverting mixer and a PLL circuit.

Modulation Insensitive PLL for Tracking Antenna Applications

This article shows practical results of a self-tracking receiving antenna array using a new phase locked loop (PLL) tracking configuration. The PLL configuration differs from other architectures, as it has the new feature of being able to directly track phase modulated signals without requiring an additional unmodulated pilot carrier to be present. The PLLs are used within the antenna array to produce a constant phase intermediate frequency (IF) for each antenna element. These IF's can then be combined in phase, regardless of the angle of arrival of the signal, thus utilizing the antennas array factor. The article's main focus is on the phase jitter performance of the modulation insensitive PLL carrier recovery when tracking phase modulated signals of low signal to noise ratio. From this analysis, it is concluded that the new architecture, when optimally designed, can produce phase jitter performance close to that of a conventional tracking PLL.