Análisis de prestaciones de procesadores multi-core y multi-thread

Los procesadores multi-core y el multi-threading por hardware permiten aumentar el rendimiento de las aplicaciones. Por un lado, los procesadores multi-core combinan 2 o más procesadores en un mismo chip. Por otro lado, el multi-threading por hardware es una técnica que incrementa la utilización de los recursos del procesador. Este trabajo presenta un análisis de rendimiento de los resultados obtenidos en dos aplicaciones, multiplicación de matrices densas y transformada rápida de Fourier. Ambas aplicaciones se han ejecutado en arquitecturas multi-core que explotan el paralelismo a nivel de thread pero con un modelo de multi-threading diferente. Los resultados obtenidos muestran la importancia de entender y saber analizar el efecto del multi-core y multi-threading en el rendimiento.

Program hosting in communications environment with Reactor and thread pool approach

In this thesis concurrent communication event handling is implemented using thread pool approach. Concurrent events are handled with a Reactor design pattern and multithreading is implemented using a Leader/Followers design pattern. Main focus is to evaluate behaviour of implemented model by different numbers of concurrent connections and amount of used threads. Furthermore, model feasibility in a PeerHood middleware is evaluated. Implemented model is evaluated with created test environment which enables concurrent message sending from multiple connections to the system under test. Messages round trip times are measured in the tester application. In the evaluation processing delay into system is simulated and influence of delay to the average round trip time is analysed.

Thread Scheduling Mechanisms for Multiple-Context Parallel Processors

Scheduling tasks to efficiently use the available processor resources is crucial to minimizing the runtime of applications on shared-memory parallel processors. One factor that contributes to poor processor utilization is the idle time caused by long latency operations, such as remote memory references or processor synchronization operations. One way of tolerating this latency is to use a processor with multiple hardware contexts that can rapidly switch to executing another thread of computation whenever a long latency operation occurs, thus increasing processor utilization by overlapping computation with communication. Although multiple contexts are effective for tolerating latency, this effectiveness can be limited by memory and network bandwidth, by cache interference effects among the multiple contexts, and by critical tasks sharing processor resources with less critical tasks. This thesis presents techniques that increase the effectiveness of multiple contexts by intelligently scheduling threads to make more efficient use of processor pipeline, bandwidth, and cache resources. This thesis proposes thread prioritization as a fundamental mechanism for directing the thread schedule on a multiple-context processor. A priority is assigned to each thread either statically or dynamically and is used by the thread scheduler to decide which threads to load in the contexts, and to decide which context to switch to on a context switch. We develop a multiple-context model that integrates both cache and network effects, and shows how thread prioritization can both maintain high processor utilization, and limit increases in critical path runtime caused by multithreading. The model also shows that in order to be effective in bandwidth limited applications, thread prioritization must be extended to prioritize memory requests. We show how simple hardware can prioritize the running of threads in the multiple contexts, and the issuing of requests to both the local memory and the network. Simulation experiments show how thread prioritization is used in a variety of applications. Thread prioritization can improve the performance of synchronization primitives by minimizing the number of processor cycles wasted in spinning and devoting more cycles to critical threads. Thread prioritization can be used in combination with other techniques to improve cache performance and minimize cache interference between different working sets in the cache. For applications that are critical path limited, thread prioritization can improve performance by allowing processor resources to be devoted preferentially to critical threads. These experimental results show that thread prioritization is a mechanism that can be used to implement a wide range of scheduling policies.

ADAM: A Decentralized Parallel Computer Architecture Featuring Fast Thread and Data Migration and a Uniform Hardware Abstraction

The furious pace of Moore's Law is driving computer architecture into a realm where the the speed of light is the dominant factor in system latencies. The number of clock cycles to span a chip are increasing, while the number of bits that can be accessed within a clock cycle is decreasing. Hence, it is becoming more difficult to hide latency. One alternative solution is to reduce latency by migrating threads and data, but the overhead of existing implementations has previously made migration an unserviceable solution so far. I present an architecture, implementation, and mechanisms that reduces the overhead of migration to the point where migration is a viable supplement to other latency hiding mechanisms, such as multithreading. The architecture is abstract, and presents programmers with a simple, uniform fine-grained multithreaded parallel programming model with implicit memory management. In other words, the spatial nature and implementation details (such as the number of processors) of a parallel machine are entirely hidden from the programmer. Compiler writers are encouraged to devise programming languages for the machine that guide a programmer to express their ideas in terms of objects, since objects exhibit an inherent physical locality of data and code. The machine implementation can then leverage this locality to automatically distribute data and threads across the physical machine by using a set of high performance migration mechanisms. An implementation of this architecture could migrate a null thread in 66 cycles -- over a factor of 1000 improvement over previous work. Performance also scales well; the time required to move a typical thread is only 4 to 5 times that of a null thread. Data migration performance is similar, and scales linearly with data block size. Since the performance of the migration mechanism is on par with that of an L2 cache, the implementation simulated in my work has no data caches and relies instead on multithreading and the migration mechanism to hide and reduce access latencies.

Learning Commonsense Categorical Knowledge in a Thread Memory System

If we are to understand how we can build machines capable of broad purpose learning and reasoning, we must first aim to build systems that can represent, acquire, and reason about the kinds of commonsense knowledge that we humans have about the world. This endeavor suggests steps such as identifying the kinds of knowledge people commonly have about the world, constructing suitable knowledge representations, and exploring the mechanisms that people use to make judgments about the everyday world. In this work, I contribute to these goals by proposing an architecture for a system that can learn commonsense knowledge about the properties and behavior of objects in the world. The architecture described here augments previous machine learning systems in four ways: (1) it relies on a seven dimensional notion of context, built from information recently given to the system, to learn and reason about objects' properties; (2) it has multiple methods that it can use to reason about objects, so that when one method fails, it can fall back on others; (3) it illustrates the usefulness of reasoning about objects by thinking about their similarity to other, better known objects, and by inferring properties of objects from the categories that they belong to; and (4) it represents an attempt to build an autonomous learner and reasoner, that sets its own goals for learning about the world and deduces new facts by reflecting on its acquired knowledge. This thesis describes this architecture, as well as a first implementation, that can learn from sentences such as ``A blue bird flew to the tree'' and ``The small bird flew to the cage'' that birds can fly. One of the main contributions of this work lies in suggesting a further set of salient ideas about how we can build broader purpose commonsense artificial learners and reasoners.

Anion-templated assembly of pseudorotaxanes: importance of anion template, strength of ion-pair thread association, and macrocycle ring size

A wide range of pseuclorotaxane assemblies containing positively charged pyridinium, pyridinium nicotinamide, imidazolium, benzimidazolium and guanidinium threading components, and macrocyclic isophthalamide polyether ligands have been prepared using a general anion templation procedure. In noncompetitive solvent media, coupling halide anion recognition by a macrocyclic ligand with ion-pairing between the halide anion and a strongly associated cation provides the driving force for interpenetration. Extensive solution H-1 NMR binding studies, thermodynamic investigations, and single-crystal X-ray structure determinations reveal that the nature of the halide anion template, strength of the ion-pairing between the anion template and the cationic threading component, and to a lesser extent favorable second sphere pi-pi aromatic stacking interactions between the positively charged threading component and macrocyclic ligand, together with macrocyclic ring size, affect the efficacy of pseudorotaxane formation.

MPJ express: Towards thread safe Java HPC

MPJ Express is a thread-safe Java messaging library that provides a full implementation of the mpiJava 1.2 API specification. This specification defines a MPI-like bindings for the Java language. We have implemented two communication devices as part of our library, the first, called niodev is based on the Java New I/O package and the second, called mxdev is based on the Myrinet eXpress library MPJ Express comes with an experimental runtitne, which allows portable bootstrapping of Java Virtual Machines across a cluster or network of computers. In this paper we describe the implementation of MPJ Express. Also, we present a performance comparison against various other C and Java messaging systems. A beta version of MPJ Express was released in September 2005.

Extending the golden thread? Criminalisation and the presumption of innocence

It seems to be widely accepted that the presumption of innocence, and the attendant standard of 'beyond reasonable doubt' properly apply in the courtroom as a procedural principle directly grounded in the moral imperative to avoid punishing those who should not be punished. In this article I argue that if this is correct, then we ought be as careful about what we criminalise, as we are about who we punish, since people can be wrongfully punished by criminalisation errors as well as by conviction errors.

Evidence that the Ceratobasidium-like white-thread blight and black rot fungal pathogens from persimmon and tea crops in the Brazilian Atlantic Forest agroecosystem are two distinct phylospecies

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Comparison of variable-thread tapered implant designs to a standard tapered implant design after immediate loading. A 3-year multicentre randomised controlled trial

This randomised, controlled multicentre trial aimed at comparing two versions of a variable-thread dental implant design to a standard tapered dental implant design in cases of immediate functional loading for 36 months after loading.

Randomized controlled trial comparing a variable-thread novel tapered and a standard tapered implant: interim one-year results

STATEMENT OF PROBLEM: A tapered implant with continuously changing threads purported to provide stable tissue support and allow immediate function has been developed. Treatment success and stabilization of supporting tissues over time require documentation. PURPOSE: The purpose of this prospective, randomized, controlled, multicenter study was to evaluate changes in bone level and soft tissue behavior between the novel implant (NobelActive/NA) and a standard tapered implant (NobelReplace Tapered Groovy/NR) with regard to immediate function. MATERIAL AND METHODS: A total of 177 patients randomly allocated to 3 treatment groups (2 different test implant groups: NA Internal (n=117; internal connection) and External (n=82), and 1 standard treatment group, NR (n=126)) received 325 implants. Implants were placed into healed sites, and all but 6 implants were immediately nonocclusally loaded. Clinical and radiographic evaluations of treatment success, crestal bone levels, and soft tissue changes were performed at the time of placement and after 3, 6, and 12 months. Log-Rank test was used to analyze the differences in survival rate. Marginal bone level was compared using the Kruskal-Wallis test and Mann-Whitney U-test (alpha=.05). RESULTS: One-year cumulative survival rates were comparable (96.6% for NA Internal; 96.3% for NA External; 97.6% for NR; P=.852; Log-Rank). Mean (SD) change in bone level was -0.95 mm (1.37) for NA Internal, -0.64 mm (0.97) for NA External, and -0.63 mm (1.18) for NR (P=.589; Kruskal-Wallis). Stable soft tissues and significantly increased papilla scores (P<.001; Wilcoxon signed-rank) were observed for all implant types. CONCLUSIONS: The novel implants showed high survival rates as well as stable bone and soft tissue levels after 1 year, and may be recommended for clinical use, even under immediate function.