989 resultados para thermal management


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MultiProcessor Systems-on-Chip (MPSoC) are the core of nowadays and next generation computing platforms. Their relevance in the global market continuously increase, occupying an important role both in everydaylife products (e.g. smartphones, tablets, laptops, cars) and in strategical market sectors as aviation, defense, robotics, medicine. Despite of the incredible performance improvements in the recent years processors manufacturers have had to deal with issues, commonly called “Walls”, that have hindered the processors development. After the famous “Power Wall”, that limited the maximum frequency of a single core and marked the birth of the modern multiprocessors system-on-chip, the “Thermal Wall” and the “Utilization Wall” are the actual key limiter for performance improvements. The former concerns the damaging effects of the high temperature on the chip caused by the large power densities dissipation, whereas the second refers to the impossibility of fully exploiting the computing power of the processor due to the limitations on power and temperature budgets. In this thesis we faced these challenges by developing efficient and reliable solutions able to maximize performance while limiting the maximum temperature below a fixed critical threshold and saving energy. This has been possible by exploiting the Model Predictive Controller (MPC) paradigm that solves an optimization problem subject to constraints in order to find the optimal control decisions for the future interval. A fully-distributedMPC-based thermal controller with a far lower complexity respect to a centralized one has been developed. The control feasibility and interesting properties for the simplification of the control design has been proved by studying a partial differential equation thermal model. Finally, the controller has been efficiently included in more complex control schemes able to minimize energy consumption and deal with mixed-criticalities tasks

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A novel and new thermal management technology for advanced ceramic microelectronic packages has been developed incorporating miniature heat pipes embedded in the ceramic substrate. The heat pipes use an axially grooved wick structure and water as the working fluid. Prototype substrate/heat pipe systems were fabricated using high temperature co-fired ceramic (alumina). The heat pipes were nominally 81 mm in length, 10 mm in width, and 4 mm in height, and were charged with approximately 50–80 μL of water. Platinum thick film heaters were fabricated on the surface of the substrate to simulate heat dissipating electronic components. Several thermocouples were affixed to the substrate to monitor temperature. One end of the substrate was affixed to a heat sink maintained at constant temperature. The prototypes were tested and shown to successful and reliably operate with thermal loads over 20 Watts, with thermal input from single and multiple sources along the surface of the substrate. Temperature distributions are discussed for the various configurations and the effective thermal resistance of the substrate/heat pipe system is calculated. Finite element analysis was used to support the experimental findings and better understand the sources of the system's thermal resistance. ^

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Fueled by increasing human appetite for high computing performance, semiconductor technology has now marched into the deep sub-micron era. As transistor size keeps shrinking, more and more transistors are integrated into a single chip. This has increased tremendously the power consumption and heat generation of IC chips. The rapidly growing heat dissipation greatly increases the packaging/cooling costs, and adversely affects the performance and reliability of a computing system. In addition, it also reduces the processor's life span and may even crash the entire computing system. Therefore, dynamic thermal management (DTM) is becoming a critical problem in modern computer system design. Extensive theoretical research has been conducted to study the DTM problem. However, most of them are based on theoretically idealized assumptions or simplified models. While these models and assumptions help to greatly simplify a complex problem and make it theoretically manageable, practical computer systems and applications must deal with many practical factors and details beyond these models or assumptions. The goal of our research was to develop a test platform that can be used to validate theoretical results on DTM under well-controlled conditions, to identify the limitations of existing theoretical results, and also to develop new and practical DTM techniques. This dissertation details the background and our research efforts in this endeavor. Specifically, in our research, we first developed a customized test platform based on an Intel desktop. We then tested a number of related theoretical works and examined their limitations under the practical hardware environment. With these limitations in mind, we developed a new reactive thermal management algorithm for single-core computing systems to optimize the throughput under a peak temperature constraint. We further extended our research to a multicore platform and developed an effective proactive DTM technique for throughput maximization on multicore processor based on task migration and dynamic voltage frequency scaling technique. The significance of our research lies in the fact that our research complements the current extensive theoretical research in dealing with increasingly critical thermal problems and enabling the continuous evolution of high performance computing systems.

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A novel and new thermal management technology for advanced ceramic microelectronic packages has been developed incorporating miniature heat pipes embedded in the ceramic substrate. The heat pipes use an axially grooved wick structure and water as the working fluid. Prototype substrate/heat pipe systems were fabricated using high temperature co-fired ceramic (alumina). The heat pipes were nominally 81 mm in length, 10 mm in width, and 4 mm in height, and were charged with approximately 50-80 mL of water. Platinum thick film heaters were fabricated on the surface of the substrate to simulate heat dissipating electronic components. Several thermocouples were affixed to the substrate to monitor temperature. One end of the substrate was affixed to a heat sink maintained at constant temperature. The prototypes were tested and shown to successful and reliably operate with thermal loads over 20 Watts, with thermal input from single and multiple sources along the surface of the substrate. Temperature distributions are discussed for the various configurations and the effective thermal resistance of the substrate/heat pipe system is calculated. Finite element analysis was used to support the experimental findings and better understand the sources of the system's thermal resistance.

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The aim of this work is to present a methodology to develop cost-effective thermal management solutions for microelectronic devices, capable of removing maximum amount of heat and delivering maximally uniform temperature distributions. The topological and geometrical characteristics of multiple-story three-dimensional branching networks of microchannels were developed using multi-objective optimization. A conjugate heat transfer analysis software package and an automatic 3D microchannel network generator were developed and coupled with a modified version of a particle-swarm optimization algorithm with a goal of creating a design tool for 3D networks of optimized coolant flow passages. Numerical algorithms in the conjugate heat transfer solution package include a quasi-ID thermo-fluid solver and a steady heat diffusion solver, which were validated against results from high-fidelity Navier-Stokes equations solver and analytical solutions for basic fluid dynamics test cases. Pareto-optimal solutions demonstrate that thermal loads of up to 500 W/cm2 can be managed with 3D microchannel networks, with pumping power requirements up to 50% lower with respect to currently used high-performance cooling technologies.

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Transient power dissipation profiles in handheld electronic devices alternate between high and low power states depending on usage. Capacitive thermal management based on phase change materials potentially offers a fan-less thermal management for such transient profiles. However, such capacitive management becomes feasible only if there is a significant enhancement in the enthalpy change per unit volume of the phase change material since existing bulk materials such as paraffin fall short of requirements. In this thesis I propose novel nanostructured thin-film materials that can potentially exhibit significantly enhanced volumetric enthalpy change. Using fundamental thermodynamics of phase transition, calculations regarding the enhancement resulting from superheating in such thin film systems is conducted. Furthermore design of a microfabricated calorimeter to measure such enhancements is explained in detail. This work advances the state-of-art of phase change materials for capacitive cooling of handheld devices.

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Regulated Transformer Rectifier Units contain several power electronic boards to facilitate AC to DC power conversion. As these units become smaller, the number of devices on each board increases while their distance from each other decreases, making active cooling essential to maintaining reliable operation. Although it is widely accepted that liquid is a far superior heat transfer medium to air, the latter is still capable of yielding low device operating temperatures with proper heat sink and airflow design. The purpose of this study is to describe the models and methods used to design and build the thermal management system for one of the power electronic boards in a compact, high power regulated transformer rectifier unit. Maximum device temperature, available pressure drop and manufacturability were assessed when selecting the final design for testing. Once constructed, the thermal management system’s performance was experimentally verified at three different power levels.

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A new design route is proposed in order to fabricate aluminum matrix diamond-containing composite materials with optimized values of thermal conductivity (TC) for thermal management applications. The proper size ratio and proportions of particulate diamond–diamond and diamond–SiC bimodal mixtures are selected based on calculations with predictive schemes, which combine two main issues: (i) the volume fraction of the packed particulate mixtures, and (ii) the influence of different types of particulates (with intrinsically different metal/reinforcement interfacial thermal conductances) on the overall thermal conductivity of the composite material. The calculated results are validated by comparison with measurements on composites fabricated by gas pressure infiltration of aluminum into preforms of selected compositions of particle mixtures. Despite the relatively low quality (low price) of the diamond particles used in this work, outstanding values of TC are encountered: a maximum of 770 W/m K for Al/diamond–diamond and values up to 690 W/m K for Al/diamond–SiC.

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This PhD work arises from the necessity to give a contribution to the energy saving field, regarding automotive applications. The aim was to produce a multidisciplinary work to show how much important is to consider different aspects of an electric car realization: from innovative materials to cutting-edge battery thermal management systems (BTMSs), also dealing with the life cycle assessment (LCA) of the battery packs (BPs). Regarding the materials, it has been chosen to focus on carbon fiber composites as their use allows realizing light products with great mechanical properties. Processes and methods to produce carbon fiber goods have been analysed with a special attention on the university solar car Emilia 4. The work proceeds dealing with the common BTMSs on the market (air-cooled, cooling plates, heat pipes) and then it deepens some of the most innovative systems such as the PCM-based BTMSs after a previous experimental campaign to characterize the PCMs. After that, a complex experimental campaign regarding the PCM-based BTMSs has been carried on, considering both uninsulated and insulated systems. About the first category the tested systems have been pure PCM-based and copper-foam-loaded-PCM-based BTMSs; the insulated tested systems have been pure PCM-based and copper-foam-loaded-PCM-based BTMSs and both of these systems equipped with a liquid cooling circuit. The choice of lighter building materials and the optimization of the BTMS are strategies which helps in reducing the energy consumption, considering both the energy required by the car to move and the BP state of health (SOH). Focusing on this last factor, a clear explanation regarding the importance of taking care about the SOH is given by the analysis of a BP production energy consumption. This is why a final dissertation about the life cycle assessment (LCA) of a BP unit has been presented in this thesis.

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This paper presents a thermal modeling for power management of a new three-dimensional (3-D) thinned dies stacking process. Besides the high concentration of power dissipating sources, which is the direct consequence of the very interesting integration efficiency increase, this new ultra-compact packaging technology can suffer of the poor thermal conductivity (about 700 times smaller than silicon one) of the benzocyclobutene (BCB) used as both adhesive and planarization layers in each level of the stack. Thermal simulation was conducted using three-dimensional (3-D) FEM tool to analyze the specific behaviors in such stacked structure and to optimize the design rules. This study first describes the heat transfer limitation through the vertical path by examining particularly the case of the high dissipating sources under small area. First results of characterization in transient regime by means of dedicated test device mounted in single level structure are presented. For the design optimization, the thermal draining capabilities of a copper grid or full copper plate embedded in the intermediate layer of stacked structure are evaluated as a function of the technological parameters and the physical properties. It is shown an interest for the transverse heat extraction under the buffer devices dissipating most the power and generally localized in the peripheral zone, and for the temperature uniformization, by heat spreading mechanism, in the localized regions where the attachment of the thin die is altered. Finally, all conclusions of this analysis are used for the quantitative projections of the thermal performance of a first demonstrator based on a three-levels stacking structure for space application.

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Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.

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One of the most prominent industrial applications of heat transfer science and engineering has been electronics thermal control. Driven by the relentless increase in spatial density of microelectronic devices, integrated circuit chip powers have risen by a factor of 100 over the past twenty years, with a somewhat smaller increase in heat flux. The traditional approaches using natural convection and forced-air cooling are becoming less viable as power levels increase. This paper provides a high-level overview of the thermal management problem from the perspective of a practitioner, as well as speculation on the prospects for electronics thermal engineering in years to come.

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Understanding the underlying mechanisms that suppress thermal conduction in solids is of paramount importance for the targeted design of materials for thermal management and thermoelectric energy conversion applications. Bismuth copper oxychalcogenides, BiOCuQ (Q = Se, Te), are highly crystalline thermoelectric materials with an unusually low lattice thermal conductivity of approx. 0.5 Wm-1K-1, a value normally found in amorphous materials. Here we unveil the origin of the unusual thermal transport properties of these phases. First principles calculations of the vibrational properties combined with analysis of in-situ neutron diffraction data, demonstrate that weak bonding of copper atoms within the structure leads to an unexpected vibrational mode at low frequencies, which is likely to be a major contributor to the low thermal conductivity of these materials. In addition, we show that anharmonicity and the large Grüneisen parameter in these oxychalcogenides are mainly related to the low frequency copper vibrations, rather than to the Bi3+ lone pairs.