Can Cooling Technology Save Many-Core Parallel Programming from Its Programming Woes?

An abstract of this work will be presented at the Compiler, Architecture and Tools Conference (CATC), Intel Development Center, Haifa, Israel November 23, 2015.

Plasmonic nanofocusing of light in an integrated silicon photonics platform.

The capability to focus electromagnetic energy at the nanoscale plays an important role in nanoscinece and nanotechnology. It allows enhancing light matter interactions at the nanoscale with applications related to nonlinear optics, light emission and light detection. It may also be used for enhancing resolution in microscopy, lithography and optical storage systems. Hereby we propose and experimentally demonstrate the nanoscale focusing of surface plasmons by constructing an integrated plasmonic/photonic on chip nanofocusing device in silicon platform. The device was tested directly by measuring the optical intensity along it using a near-field microscope. We found an order of magnitude enhancement of the intensity at the tip's apex. The spot size is estimated to be 50 nm. The demonstrated device may be used as a building block for "lab on a chip" systems and for enhancing light matter interactions at the apex of the tip.

Hybrid integration and packaging of grating-coupled silicon photonics

This thesis covers both the packaging of silicon photonic devices with fiber inputs and outputs as well as the integration of laser light sources with these same devices. The principal challenge in both of these pursuits is coupling light into the submicrometer waveguides that are the hallmark of silicon-on-insulator (SOI) systems. Previous work on grating couplers is leveraged to design new approaches to bridge the gap between the highly-integrated domain of silicon, the Interconnected world of fiber and the active region of III-V materials. First, a novel process for the planar packaging of grating couplers with fibers is explored in detail. This technology allows the creation of easy-to-use test platforms for laser integration and also stands on its own merits as an enabling technology for next-generation silicon photonics systems. The alignment tolerances of this process are shown to be well-suited to a passive alignment process and for wafer-scale assembly. Furthermore, this technology has already been used to package demonstrators for research partners and is included in the offerings of the ePIXfab silicon photonics foundry and as a design kit for PhoeniX Software’s MaskEngineer product. After this, a process for hybridly integrating a discrete edge-emitting laser with a silicon photonic circuit using near-vertical coupling is developed and characterized. The details of the various steps of the design process are given, including mechanical, thermal, optical and electrical steps. The interrelation of these design domains is also discussed. The construction process for a demonstrator is outlined, and measurements are presented of a series of single-wavelength Fabry-Pérot lasers along with a two-section laser tunable in the telecommunications C-band. The suitability and potential of this technology for mass manufacture is demonstrated, with further opportunities for improvement detailed and discussed in the conclusion.

Development of germanium/silicon integration for near infrared detection

Silicon (Si) is the base material for electronic technologies and is emerging as a very attractive platform for photonic integrated circuits (PICs). PICs allow optical systems to be made more compact with higher performance than discrete optical components. Applications for PICs are in the area of fibre-optic communication, biomedical devices, photovoltaics and imaging. Germanium (Ge), due to its suitable bandgap for telecommunications and its compatibility with Si technology is preferred over III-V compounds as an integrated on-chip detector at near infrared wavelengths. There are two main approaches for Ge/Si integration: through epitaxial growth and through direct wafer bonding. The lattice mismatch of ~4.2% between Ge and Si is the main problem of the former technique which leads to a high density of dislocations while the bond strength and conductivity of the interface are the main challenges of the latter. Both result in trap states which are expected to play a critical role. Understanding the physics of the interface is a key contribution of this thesis. This thesis investigates Ge/Si diodes using these two methods. The effects of interface traps on the static and dynamic performance of Ge/Si avalanche photodetectors have been modelled for the first time. The thesis outlines the original process development and characterization of mesa diodes which were fabricated by transferring a ~700 nm thick layer of p-type Ge onto n-type Si using direct wafer bonding and layer exfoliation. The effects of low temperature annealing on the device performance and on the conductivity of the interface have been investigated. It is shown that the diode ideality factor and the series resistance of the device are reduced after annealing. The carrier transport mechanism is shown to be dominated by generation–recombination before annealing and by direct tunnelling in forward bias and band-to-band tunnelling in reverse bias after annealing. The thesis presents a novel technique to realise photodetectors where one of the substrates is thinned by chemical mechanical polishing (CMP) after bonding the Si-Ge wafers. Based on this technique, Ge/Si detectors with remarkably high responsivities, in excess of 3.5 A/W at 1.55 μm at −2 V, under surface normal illumination have been measured. By performing electrical and optical measurements at various temperatures, the carrier transport through the hetero-interface is analysed by monitoring the Ge band bending from which a detailed band structure of the Ge/Si interface is proposed for the first time. The above unity responsivity of the detectors was explained by light induced potential barrier lowering at the interface. To our knowledge this is the first report of light-gated responsivity for vertically illuminated Ge/Si photodiodes. The wafer bonding approach followed by layer exfoliation or by CMP is a low temperature wafer scale process. In principle, the technique could be extended to other materials such as Ge on GaAs, or Ge on SOI. The unique results reported here are compatible with surface normal illumination and are capable of being integrated with CMOS electronics and readout units in the form of 2D arrays of detectors. One potential future application is a low-cost Si process-compatible near infrared camera.

Silicon Photonics Integrated Circuits for Flexible Optical Systems

This dissertation deals with the design and the characterization of novel reconfigurable silicon-on-insulator (SOI) devices to filter and route optical signals on-chip. Design is carried out through circuit simulations based on basic circuit elements (Building Blocks, BBs) in order to prove the feasibility of an approach allowing to move the design of Photonic Integrated Circuits (PICs) toward the system level. CMOS compatibility and large integration scale make SOI one of the most promising material to realize PICs. The concepts of generic foundry and BB based circuit simulations for the design are emerging as a solution to reduce the costs and increase the circuit complexity. To validate the BB based approach, the development of some of the most important BBs is performed first. A novel tunable coupler is also presented and it is demonstrated to be a valuable alternative to the known solutions. Two novel multi-element PICs are then analysed: a narrow linewidth single mode resonator and a passband filter with widely tunable bandwidth. Extensive circuit simulations are carried out to determine their performance, taking into account fabrication tolerances. The first PIC is based on two Grating Assisted Couplers in a ring resonator (RR) configuration. It is shown that a trade-off between performance, resonance bandwidth and device footprint has to be performed. The device could be employed to realize reconfigurable add-drop de/multiplexers. Sensitivity with respect to fabrication tolerances and spurious effects is however observed. The second PIC is based on an unbalanced Mach-Zehnder interferometer loaded with two RRs. Overall good performance and robustness to fabrication tolerances and nonlinear effects have confirmed its applicability for the realization of flexible optical systems. Simulated and measured devices behaviour is shown to be in agreement thus demonstrating the viability of a BB based approach to the design of complex PICs.

Studies on the deposition and characterization of silicon oxide films for optical coating applications

Silicon oxide films were deposited by reactive evaporation of SiO. Parameters such as oxygen partial pressure and substrate temperature were varied to get variable and graded index films. Films with a refractive index in the range 1.718 to 1.465 at 550 nm have been successfully deposited. Films deposited using ionized oxygen has the refractive index 1.465 at 550 nm and good UV transmittance like bulk fused quartz. Preparation of graded index films was also investigated by changing the oxygen partial pressure during deposition. A two layer antireflection coating at 1064nm has been designed using both homogeneous and inhomogeneous films and studied their characteristics.

Transfer free suspended graphene devices on silicon using electrodeposited copper

Transfer free processes using Cu films greatly simplify the fabrication of reliable suspended graphene devices. In this paper, the authors report on the use of electrodeposited Cu films on Si for transfer free fabrication of suspended graphene devices. The quality of graphene layers on optimized electrodeposited Cu and Cu foil are found to be the same. By selectively etching the underlying Cu, the authors have realized by a transfer free process metal contacted, suspended graphene beams up to 50 mu m in length directly on Si. The suspended graphene beams do not show any increase in defect levels over the as grown state indicating the efficiency of the transfer free process. Measured room temperature electronic mobilities of up to 5200 cm(2)/V.s show that this simpler and CMOS compatible route has the potential to replace the foil based route for such suspended nano and micro electromechanical device arrays. (C) 2014 American Vacuum Society.

Fabrication and characterization of sub 100 nm period polymer gratings for photonics applications

We report on the fabrication of polymethylmethacrylate (PMMA) nanogratings on silicon (Si) and glass substrates using electron beam lithography technique. Various aspects of proximity corrections using Monte Carlo simulation have been discussed. The fabrication process parameters such as proximity gap of exposure, exposure dosage and developing conditions have been optimized for high-density PMMA nanogratings structure on Si and glass substrates. Electron beam exposure is adjusted in such a way that PMMA acts as a negative tone resist and at the same time resolution loss due to proximity effect is minimum. Both reflection and transmission-type, nanometre period gratings have been fabricated and their diffraction characteristics are evaluated.

Optoelectronic Properties of Graphene on Silicon Substrate: Effect of Defects in Graphene

Engineering of electronic energy band structure in graphene based nanostructures has several potential applications. Substrate induced bandgap opening in graphene results several optoelectronic properties due to the inter-band transitions. Various defects like structures, including Stone-Walls and higher-order defects are observed when a graphene sheet is exfoliated from graphite and in many other growth conditions. Existence of defect in graphene based nanostructures may cause changes in optoelectronic properties. Defect engineered graphene on silicon system are considered in this paper to study the tunability of optoelectronic properties. Graphene on silicon atomic system is equilibrated using molecular dynamics simulation scheme. Based on this study, we confirm the existence of a stable super-lattice. Density functional calculations are employed to determine the energy band structure for the super-lattice. Increase in the optical energy bandgap is observed with increasing of order of the complexity in the defect structure. Optical conductivity is computed as a function of incident electromagnetic energy which is also increasing with increase in the defect order. Tunability in optoelectronic properties will be useful in understanding graphene based design of photodetectors, photodiodes and tunnelling transistors.

High tuning range AlSi RF MEMS capacitors fabricated with sacrificial amorphous silicon surface micromachining

This paper reports the fabrication and electrical characterization of high tuning range AlSi RF MEMS capacitors. We present experimental results obtained by a surface micromachining process that uses dry etching of sacrificial amorphous silicon to release Al-1%Si membranes and has a low thermal budget (<450 °C) being compatible with CMOS post-processing. The proposed silicon sacrificial layer dry etching (SSLDE) process is able to provide very high Si etch rates (3-15 μm/min, depending on process parameters) with high Si: SiO2 selectivity (>10,000:1). Single- and double-air-gap MEMS capacitors, as well as some dedicated test structures needed to calibrate the electro-mechanical parameters and explore the reliability of the proposed technology, have been fabricated with the new process. S-parameter measurements from 100 MHz up to 2 GHz have shown a capacitance tuning range higher than 100% with the double-air-gap architecture. The tuning range can be enlarged with a proper DC electrical bias of the capacitor electrodes. Finally, the reported results make the proposed MEMS tuneable capacitor a good candidate for above-IC integration in communications applications. © 2004 Elsevier B.V. All rights reserved.

Assembly and inspection of liquid crystal on silicon devices

Liquid crystal on silicon (LCOS) is one of the most exciting technologies, combining the optical modulation characteristics of liquid crystals with the power and compactness of a silicon backplane. The objective of our work is to improve cell assembly and inspection methods by introducing new equipment for automated assembly and by using an optical inspection microscope. A Suss-Micro'Tec Universal device bonder is used for precision assembly and device packaging and an Olympus BX51 high resolution microscope is employed for device inspection. ©2009 Optical Society of America.

Low-temperature (≤600 °C) semi-insulating oxygen-doped silicon films by the PECVD technique for large-area power applications

This work describes the deposition, annealing and characterisation of semi-insulating oxygen-doped silicon films at temperatures compatible with polysilicon circuitry on glass. The semi-insulating layers are deposited by the plasma enhanced chemical vapour deposition technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures at a temperature of 350 °C. The as-deposited films are then furnace annealed at 600 °C which is the maximum process temperature. Raman analysis shows the as-deposited and annealed films to be completely amorphous. The most important deposition variable is the N2O SiH4 gas ratio. By varying the N2O SiH4 ratio the conductivity of the annealed films can be accurately controlled, for the first time, down to a minimum of ≈10-7Ω-1cm-1 where they exhibit a T -1 4 temperature dependence indicative of a hopping conduction mechanism. Helium dilution of the reactant gases is shown to improve both film uniformity and reproducibility. A model for the microstructure of these semi-insulating amorphous oxygen-doped silicon films is proposed to explain the observed physical and electrical properties. © 1995.

Low temperature (≤ 600°C) semi-insulating oxygen-doped silicon films by the PECVD technique for large area power applications

This work describes the annealing and characterisation of semi-insulating oxygen-doped silicon films deposited by the Plasma Enhanced Chemical Vapour Deposition (PECVD) technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures. The maximum process temperature is chosen to be compatible with large area polycrystalline silicon (poly-Si) circuitry on glass. The most important deposition variable is shown to be the N2O SiH4 gas ratio. Helium dilution results in improved film uniformity and reproducibility. Raman analysis shows the 'as-deposited' and annealed films to be completely amorphous. A model for the microstructure of these Semi-Insulating Amorphous Oxygen-doped Silicon (SIAOS) films is proposed to explain the observed physical and electrical properties. © 1995.