Dressing monitoring with a digital signal processor

Grinding is a finishing process in machining operations, and the topology of the grinding tool is responsible for producing the desired result on the surface of the machined material The tool topology is modeled in the dressing process and precision is therefore extremely important This study presents a solution in the monitoring of the dressing process, using a digital signal processor (DSP) operating in real time to detect the optimal dressing moment To confirm the monitoring efficiency by DSP, the results were compared with those of a data acquisition system (DAQ) and offline processing The method employed here consisted of analyzing the acoustic emission and electrical power signal by applying the DPO and DPKS parameters The analysis of the results allowed us to conclude that the application of the DPO and DPKS parameters can be substituted by processing of the mean acoustic emission signal, thus reducing the computational effort

Noise reduction in speech signals using a TMS320C31 digital signal processor

This paper describes a speech enhancement system (SES) based on a TMS320C31 digital signal processor (DSP) for real-time application. The SES algorithm is based on a modified spectral subtraction method and a new speech activity detector (SAD) is used. The system presents a medium computational load and a sampling rate up to 18 kHz can be used. The goal is load and a sampling rate up to 18 kHz can be used. The goal is to use it to reduce noise in an analog telephone line.

Dynamic and isometric protocols of knee extension: Effect of fatigue on the EMG signal

The objective of this study was to analyze the electromyographic (EMG) signal behavior of rectus femoris (RF), vastus medialis (VM), vastus lateralis (VL) and biceps femoris (caput longum) (BFCL) from nine women during fatiguing dynamic and isometric knee extensions tests and to determine their EMGFT (Electromyographic Fatigue Threshold). Surface electrodes, biological signal acquisition module, analogical-digital converter board and specific software were used. The RMS (Root Mean Square) values obtained from concentric phase (80 to 30 degrees) of the dynamic knee extension andfrom isometric contraction were correlated with time on each load by linear regression analysis. The respective slopes were correlated with the correspondent load to determine the EMGFT. Force (Kgf) and median frequency - MF (Hz) obtained during MIVC (Maximal Isometric Voluntary Contraction) performed before and after the fatiguing tests were calculated in Matlab environment. The results demonstrated that the endurance time decreases with higher loads the EMG amplitude increase with time and was greater at higher loads, between muscles in dynamic exercise the RF and VL showed higher slopes, and in isometric exercise the VL showed the same behavior The EMGFT values were similar in both exercises; the force values predominantly decreased after fatiguing tests; however the MF only decreased after some loads. The protocols proposed allowed standardizing protocols at least to induce the fatigue process and to determine the EMGFT as an endurance indicative, which may be used to evaluate the effectiveness of rehabilitative or training interventions indicated to reduce muscle weakness and fatigue.

Multi Processor Systems On Chip with Configurable Hardware Acceleration

The evolution of the electronics embedded applications forces electronics systems designers to match their ever increasing requirements. This evolution pushes the computational power of digital signal processing systems, as well as the energy required to accomplish the computations, due to the increasing mobility of such applications. Current approaches used to match these requirements relies on the adoption of application specific signal processors. Such kind of devices exploits powerful accelerators, which are able to match both performance and energy requirements. On the other hand, the too high specificity of such accelerators often results in a lack of flexibility which affects non-recurrent engineering costs, time to market, and market volumes too. The state of the art mainly proposes two solutions to overcome these issues with the ambition of delivering reasonable performance and energy efficiency: reconfigurable computing and multi-processors computing. All of these solutions benefits from the post-fabrication programmability, that definitively results in an increased flexibility. Nevertheless, the gap between these approaches and dedicated hardware is still too high for many application domains, especially when targeting the mobile world. In this scenario, flexible and energy efficient acceleration can be achieved by merging these two computational paradigms, in order to address all the above introduced constraints. This thesis focuses on the exploration of the design and application spectrum of reconfigurable computing, exploited as application specific accelerators for multi-processors systems on chip. More specifically, it introduces a reconfigurable digital signal processor featuring a heterogeneous set of reconfigurable engines, and a homogeneous multi-core system, exploiting three different flavours of reconfigurable and mask-programmable technologies as implementation platform for applications specific accelerators. In this work, the various trade-offs concerning the utilization multi-core platforms and the different configuration technologies are explored, characterizing the design space of the proposed approach in terms of programmability, performance, energy efficiency and manufacturing costs.

All-optical nonlinear signal processing at a RZ receiver

We propose a novel all-optical signal processor for use at a return-to-zero receiver utilising loop mirror intensity filtering and nonlinear pulse broadening in normal dispersion fibre. The device offers reamplification and cleaning up of the optical signals, and phase margin improvement. The efficiency of the technique is demonstrated by application to 40 Gbit/s data transmission.

Digital signal processing implementation for near real-time wavelet transformation system for binary images

Communication has become an essential function in our civilization. With the increasing demand for communication channels, it is now necessary to find ways to optimize the use of their bandwidth. One way to achieve this is by transforming the information before it is transmitted. This transformation can be performed by several techniques. One of the newest of these techniques is the use of wavelets. Wavelet transformation refers to the act of breaking down a signal into components called details and trends by using small waveforms that have a zero average in the time domain. After this transformation the data can be compressed by discarding the details, transmitting the trends. In the receiving end, the trends are used to reconstruct the image. In this work, the wavelet used for the transformation of an image will be selected from a library of available bases. The accuracy of the reconstruction, after the details are discarded, is dependent on the wavelets chosen from the wavelet basis library. The system developed in this thesis takes a 2-D image and decomposes it using a wavelet bank. A digital signal processor is used to achieve near real-time performance in this transformation task. A contribution of this thesis project is the development of DSP-based test bed for the future development of new real-time wavelet transformation algorithms.

Embedded DSP-Based Compact Fuzzy System and Its Application for Induction-Motor V/f Speed Control

This paper presents a compact embedded fuzzy system for three-phase induction-motor scalar speed control. The control strategy consists in keeping constant the voltage-frequency ratio of the induction-motor supply source. A fuzzy-control system is built on a digital signal processor, which uses speed error and speed-error variation to change both the fundamental voltage amplitude and frequency of a sinusoidal pulsewidth modulation inverter. An alternative optimized method for embedded fuzzy-system design is also proposed. The controller performance, in relation to reference and load-torque variations, is evaluated by experimental results. A comparative analysis with conventional proportional-integral controller is also achieved.

Limiting Internal Supply Voltage Spikes in DC-DC Converters

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.

An Efficient Long Distance Echo Canceller

This paper describes an implementation of a long distance echo canceller, operating on full-duplex with hands-free and in real-time with a single Digital Signal Processor (DSP). The proposed solution is based on short length adaptive filters centered on the positions of the most significant echoes, which are tracked by time delay estimators, for which we use a new approach. To deal with double talking situations a speech detector is employed. The floating-point DSP TMS320C6713 from Texas Instruments is used with software written in C++, with compiler optimizations for fast execution. The resulting algorithm enables long distance echo cancellation with low computational requirements, suited for embbeded systems. It reaches greater echo return loss enhancement and shows faster convergence speed when compared to the conventional approach. The experimental results approach the CCITT G.165 recommendation levels.

Análise e implementação de filtros e controladores num sistema de processamento digital de sinal

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Automação e Electrónica Industrial

Desenvolvimento de um Controlador com DSP para um Motor CA de 30 kW para o CEPIUM

Dissertação de mestrado integrado em Engenharia Eletrónica Industrial e Computadores

Intracellular nanomanipulation by a photonic-force microscope with real-time acquisition of a 3D stiffness matrix.

A traditional photonic-force microscope (PFM) results in huge sets of data, which requires tedious numerical analysis. In this paper, we propose instead an analog signal processor to attain real-time capabilities while retaining the richness of the traditional PFM data. Our system is devoted to intracellular measurements and is fully interactive through the use of a haptic joystick. Using our specialized analog hardware along with a dedicated algorithm, we can extract the full 3D stiffness matrix of the optical trap in real time, including the off-diagonal cross-terms. Our system is also capable of simultaneously recording data for subsequent offline analysis. This allows us to check that a good correlation exists between the classical analysis of stiffness and our real-time measurements. We monitor the PFM beads using an optical microscope. The force-feedback mechanism of the haptic joystick helps us in interactively guiding the bead inside living cells and collecting information from its (possibly anisotropic) environment. The instantaneous stiffness measurements are also displayed in real time on a graphical user interface. The whole system has been built and is operational; here we present early results that confirm the consistency of the real-time measurements with offline computations.

Moottorinohjaukseen tarkoitettujen signaaliprosessoreiden vertailu

Työssä tarkastellaan kolmen eri valmistajan signaaliprosessoriperheitä. Työn tavoitteena on tutkia prosessoreiden teknistä soveltuvuutta suunnitteilla olevaan taajuusmuuttajatuoteperheeseen. Työn alkuosassa käydään taajuusmuuttajan rakenne läpi ja selostetaan oikosulkumoottorin yleisimmät ohjausmenetelmät. Työssä selvitetään myös signaaliprosessorin ja integroitujen oheispiirien toimintaa. Työn painopiste prosessoreiden teknisten ominaisuuksien vertailussa. Työssä on vertailtu muun muassa prosessoreiden sisäistä rakennetta, käskykantojen ominaisuuksia, keskeytysten palveluun kuluvaa aikaa ja oheispiirien ominaisuuksia. Oheispiirien, erityisesti analogiadigitaalimuuntimen halutunlainen toiminta on moottorinohjausohjelmiston kannalta tärkeää. Työhön sisällytetyt prosessoriperheet on pisteytetty tarkasteltujen ominaisuuksien osalta. Vertailun tuloksena on esitetty haettuun tarkoitukseen teknisesti soveltuvin prosessoriperhe ja prosessorityyppi. Työssä ei kuitenkaan voida antaa yleistä paremmuusjärjestystä tutkituille prosessoreille.

Sulautetun moniprosessorijärjestelmän suunnittelu sähkömoottorien ohjaus- ja valvontatarpeisiin

Universal Converter (UNICON) –projektin osana suunniteltiin sähkömoottorikäyttöjen ohjaukseen ja mittaukseen soveltuva digitaaliseen signaaliprosessoriin (DSP) pohjautuva sulautettu järjestelmä. Riittävän laskentatehon varmistamiseksi päädyttiin käyttämään moniprosessorijärjestelmää. Prosessorijärjestelmässä käytettävää DSP-piiriä valittaessa valintaperusteina olivat piirien tarjoama prosessointiteho ja moniprosessorituki. Analog Devices:n SHARC-sarjan DSP-piirit täyttivät parhaiten asetetut vaatimukset: Ne tarjoavat tehokkaan käskykannan lisäksi suuren sisäisen muistin ja sisäänrakennetun moniprosessorituen. Järjestelmän mittalaiteluonteisuudesta johtuen keskeinen suunnitteluparametri oli luoda nopeat tiedonsiirtoyhteydet mittausantureilta DSP-järjestelmään. Tämä toteutettiin käyttäen ohjelmointavia FPGA-logiikkapiirejä digitaalimuotoisen mittausdatan vastaanotossa ja esikäsittelyssä. Tiedonsiirtoyhteys PC-tietokoneelle toteutettiin käyttäen erityistä liityntäkorttia DSP-järjestelmän ja PC-tietokoneen välillä. Liityntäkortin päätehtävänä on puskuroida siirrettävä data. Järjestelyllä estetään PC-tietokoneen vaikutus DSP-järjestelmän toimintaan, jotta kyetään takaamaan järjestelmän reaaliaikainen toiminta kaikissa olosuhteissa.

Methods of Design and Testing of Real Time Systems

Teollusuussovelluksissa vaaditaan nykyisin yhä useammin reaaliaikaista tiedon käsittelyä. Luotettavuus on yksi tärkeimmistä reaaliaikaiseen tiedonkäsittelyyn kykenevän järjestelmän ominaisuuksista. Sen saavuttamiseksi on sekä laitteisto, että ohjelmisto testattava. Tämän työn päätavoitteena on laitteiston testaaminen ja laitteiston testattavuus, koska luotettava laitteistoalusta on perusta tulevaisuuden reaaliaikajärjestelmille. Diplomityössä esitetään digitaaliseen signaalinkäsittelyyn soveltuvan prosessorikortin suunnittelu. Prosessorikortti on tarkoitettu sähkökoneiden ennakoivaa kunnonvalvontaa varten. Uusimmat DFT (Desing for Testability) menetelmät esitellään ja niitä sovelletaan prosessorikortin sunnittelussa yhdessä vanhempien menetelmien kanssa. Kokemukset ja huomiot menetelmien soveltuvuudesta raportoidaan työn lopussa. Työn tavoitteena on kehittää osakomponentti web -pohjaiseen valvontajärjestelmään, jota on kehitetty Sähkötekniikan osastolla Lappeenrannan teknillisellä korkeakoululla.