MOWER : A NEW DESIGN FOR NON-BLOCKING MISPREDICTION RECOVERY

Mower is a micro-architecture technique which targets branch misprediction penalties in superscalar processors. It speeds-up the misprediction recovery process by dynamically evicting stale instructions and fixing the RAT (Register Alias Table) using explicit branch dependency tracking. Tracking branch dependencies is accomplished by using simple bit matrices. This low-overhead technique allows overlapping of the recovery process with instruction fetching, renaming and scheduling from the correct path. Our evaluation of the mechanism indicates that it yields performance very close to ideal recovery and provides up to 5% speed-up and 2% reduction in power consumption compared to a traditional recovery mechanism using a reorder buffer and a walker. The simplicity of the mechanism should permit easy implementation of Mower in an actual processor.

Formalising progress properties of non-blocking programs

A non-blocking program is one that uses non-blocking primitives, such as load-linked/store-conditional and compare-and-swap, for synchronisation instead of locks so that no process is ever blocked. According to their progress properties, non-blocking programs may be classified as wait-free, lock-free or obstruction-free. However, a precise description of these properties does not exist and it is not unusual to find a definition that is ambiguous or even incorrect. We present a formal definition of the progress properties so that any confusion is removed. The formalisation also allows one to prove the widely believed presumption that wait-freedom is a special case of lock-freedom, which in turn is a special case of obstruction-freedom.

Dimensions of coupling in middleware

It is well accepted that different types of distributed architectures require different degrees of coupling. For example, in client-server and three-tier architectures, application components are generally tightly coupled, both with one another and with the underlying middleware. Meanwhile, in off-line transaction processing, grid computing and mobile applications, the degree of coupling between application components and with the underlying middleware needs to be minimized. Terms such as ‘synchronous’, ‘asynchronous’, ‘blocking’, ‘non-blocking’, ‘directed’, and ‘non-directed’ are often used to refer to the degree of coupling required by an architecture or provided by a middleware. However, these terms are used with various connotations. Although various informal definitions have been provided, there is a lack of an overarching formal framework to unambiguously communicate architectural requirements with respect to (de-)coupling. This article addresses this gap by: (i) formally defining three dimensions of (de-)coupling; (ii) relating these dimensions to existing middleware; and (iii) proposing notational elements to represent various coupling integration patterns. This article also discusses a prototype that demonstrates the feasibility of its implementation.

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router

A polymorphic ASIC is a runtime reconfigurable hardware substrate comprising compute and communication elements. It is a ldquofuture proofrdquo custom hardware solution for multiple applications and their derivatives in a domain. Interoperability between application derivatives at runtime is achieved through hardware reconfiguration. In this paper we present the design of a single cycle Network on Chip (NoC) router that is responsible for effecting runtime reconfiguration of the hardware substrate. The router design is optimized to avoid FIFO buffers at the input port and loop back at output crossbar. It provides virtual channels to emulate a non-blocking network and supports a simple X-Y relative addressing scheme to limit the control overhead to 9 bits per packet. The 8times8 honeycomb NoC (RECONNECT) implemented in 130 nm UMC CMOS standard cell library operates at 500 MHz and has a bisection bandwidth of 28.5 GBps. The network is characterized for random, self-similar and application specific traffic patterns that model the execution of multimedia and DSP kernels with varying network loads and virtual channels. Our implementation with 4 virtual channels has an average network latency of 24 clock cycles and throughput of 62.5% of the network capacity for random traffic. For application specific traffic the latency is 6 clock cycles and throughput is 87% of the network capacity.

Saturation throughput analysis of an input queueing ATM switch with multiclass bursty traffic

In this paper we consider an N x N non-blocking, space division ATM switch with input cell queueing. At each input, the cell arrival process comprises geometrically distributed bursts of consecutive cells for the various outputs. Motivated by the fact that some input links may be connected to metropolitan area networks, and others directly to B-ISDN terminals, we study the situation where there are two classes of inputs with different values of mean burst length. We show that when inputs contend for an output, giving priority to an input with smaller expected burst length yields a saturation throughput larger than if the reverse priority is given. Further, giving priority to less bursty traffic can give better throughput than if all the inputs were occupied by this less bursty traffic. We derive the asymptotic (as N --> infinity) saturation throughputs for each priority class.

基于双面反射镜的N×N光开关的特性分析和实验研究

报道了基于双面反射镜的N×N光开关器件。介绍了使用双面反射镜的2×2, 4×4光开关的集成光路设计和工作原理; 采用Benes网络, 以2×2和4×4光开关为基本单元的N×N光开关器件的整体结构, 并根据“一笔画”原理, 分析了4×4, 8×8和16×16光开关矩阵的可重排无阻塞特性和光开关矩阵的光路选择算法。最后, 基于2×2, 4×4光开关技术制备了16×16光开关矩阵。测试表明, 该器件具有良好的插入损耗、回波损耗、串扰和开关时间等性能, 从而验证了设计思想和工艺的可行性。在基于双面反射镜的光开关矩

单块晶体集成的N×N纵横开关网络及其控制算法

设计了一种单块晶体集成的n×n纵横开关(Crossbar)网络。通过综合考虑晶体的双折射和全内双反射现象,以及晶体的电光效应,将构成n×n纵横开关网络的所有单元器件都集成到一块具有电光效应的双折射晶体上。同时,给出了该网络的控制算法,通过对开关工作状态的控制,可以实现任意输入输出通道之间的无阻塞连接。这种单块晶体集成的纵横开关网络具有能量损耗低、无阻塞、易安装、抗干扰等优点,适合于全光网络发展的需要。

Polymer waveguide-based backplanes for board-level optical interconnects

Optical interconnects are increasingly considered for use in high-performance electronic systems. Multimode polymer waveguides are a promising technology for the formation of optical backplane as they enable cost-effective integration of optical links onto standard printed circuit boards. In this paper, two different types of polymer waveguide-based optical backplanes are presented. The first one implements a passive shuffle architecture enabling non-blocking on-board optical interconnection between different cards/modules, while the second one deploys a regenerative bus architecture allowing the interconnection of an arbitrary number of electrical cards over a common optical bus. The polymer materials and the multimode waveguide components used to form the optical backplanes are presented, while details of the interconnection architectures and design of the backplanes are described. Proof-of-principle demonstrators fabricated onto low-cost FR4 substrates, including a 10-card 1 Tb/s-capacity passive shuffle router and 4-channel 3-card polymeric bus modules, are reported and their optical performance characteristics are presented. Low-loss, low-crosstalk on-board interconnection is achieved and error-free (BER10 12) 10 Gb/s communication between different card/module interfaces is demonstrated in both polymeric backplane systems. © 2012 IEEE.

SOI optical switch matrix integrated with spot size converter (SSC) and total internal reflection (TIR) mirrors

SOI (Silicon on Insulator) based photonic devices has attracted more and more attention in the recent years. Integration of SOI optical switch matrix with isolating grooves, total internal reflection (TIR) mirrors and spot size converter (SSC) was studied. A folding re-arrangeable non-blocking 4x4 optical switch matrix and a blocking 16x16 matrix with TIR mirrors and SSC were fabricated on SOI wafer. The performaces, including extinction ratio and the crosstalk, are better than before. The insertion loss and the polarization dependent loss (PDL) at 1.55 mu m increase slightly with longer device length, more bend and intersecting waveguides. The insertion losses decrease 2 similar to 3 dB when anti-reflection films are added in the ends of the devices. The rise and fall times of the devices are 2.1 mu s and 2.3 mu s, respectively.

Recent progresses of SOI-based photonic devices - art. no. 60201R

SOI (Silicon on Insulator) based photonic devices, including stimulated emission from Si diode, RCE (Resonant Cavity Enhanced) photodiode with quantum structure, MOS (Metal Oxide Semiconductor) optical modulator with high frequency, SOI optical matrix switch and wavelength tunable filter are reviewed in the paper. The emphasis will be played on our recent results of SOI-based thermo-optic waveguide matrix switch with low insertion loss and fast response. A folding re-arrangeable non-blocking 4x4 matrix switch with total internal reflection (TIR) mirrors and a first blocking 16 x 16 matrix were fabricated on SOI wafer. The extinction ratio and the crosstalk are better. The insertion loss and the polarization dependent loss (PDL) at 1.55 mu m increase slightly with longer device length and more bend and intersecting waveguides. The insertion losses are expected to decrease 2-3 dB when anti-reflection films are added in the ends of the devices. The rise and fall times of the devices are 2.1 mu s and 2.3 mu s, respectively.

Strategy-proofness and essentially single-valued cores revisited

We consider general allocation problems with indivisibilities where agents' preferences possibly exhibit externalities. In such contexts many different core notions were proposed. One is the gamma-core whereby blocking is only allowed via allocations where the non-blocking agents receive their endowment. We show that if there exists an allocation rule satisfying ‘individual rationality’, ‘efficiency’, and ‘strategy-proofness’, then for any problem for which the gamma-core is non-empty, the allocation rule must choose a gamma-core allocation and all agents are indifferent between all allocations in the gamma-core. We apply our result to housing markets, coalition formation and networks.

Performance analysis of interconnection networks for multi-cluster systems

With the current popularity of cluster computing systems, it is increasingly important to understand the capabilities and potential performance of various interconnection networks. In this paper, we propose an analytical model for studying the capabilities and potential performance of interconnection networks for multi-cluster systems. The model takes into account stochastic quantities as well as network heterogeneity in bandwidth and latency in each cluster. Also, blocking and non-blocking network architecture model is proposed and are used in performance analysis of the system. The model is validated by constructing a set of simulators to simulate different types of clusters, and by comparing the modeled results with the simulated ones.