Bidirectional nonreciprocal wavelength-interleaving coherent fiber transversal filter

A bidirectional nonreciprocal wavelength-interleaving filter based on an optically coherent high birefringence fiber transversal filter structure is demonstrated. Stable, low loss, low dispersion, and high isolation operation is demonstrated with reconfigurable transfer characteristics for interleaved channel spacing of 0.8 nm.

A nonreciprocal wavelength-interleaving bidirectional coherent fiber transversal filter

A bidirectional nonreciprocal wavelength-interleaving filter based on an optically coherent high birefringence fiber transversal filter structure is demonstrated. Stable, low loss operation is achieved with reconfigurable transfer characteristics for interleaved channel spacing of 0.8 nm with >30 dB isolation and ultra-low chromatic dispersion.

Bidirectional nonreciprocal wavelength-interleaving coherent fiber transversal filter

A bidirectional nonreciprocal wavelength-interleaving filter based on an optically coherent high birefringence fiber transversal filter structure is demonstrated. Stable, low loss, low dispersion, and high isolation operation is demonstrated with reconfigurable transfer characteristics for interleaved channel spacing of 0.8 nm.

Fracture Toughening and Self-Healing of Composite Laminates by Nanofibrous Mats Interleaving

Composite laminates present important advantages compared to conventional monolithic materials, mainly because for equal stiffness and strength they have a weight up to four times lower. However, due to their ply-by-ply nature, they are susceptible to delamination, whose propagation can bring the structure to a rapid catastrophic failure. In this thesis, in order to increase the service life of composite materials, two different approaches were explored: increase the intrinsic resistance of the material or confer to them the capability of self-repair. The delamination has been hindered through interleaving the composite laminates with polymeric nanofibers, which completed the hierarchical reinforcement scale of the composite. The manufacturing process for the integration of the nanofibrous mat in the laminate was optimized, resulting in an enhancement of mode I fracture toughness up to 250%. The effect of the geometrical dimensions of the nano-reinforcement on the architecture of the micro one (UD and woven laminates) was studied on mode I and II. Moreover, different polymeric materials were employed as nanofibrous reinforcement (Nylon 66 and polyvinylidene fluoride). The nano toughening mechanism was studied by micrograph analysis of the crack path and SEM analysis of the fracture surface. The fatigue behavior to the onset of the delamination and the crack growth rate for woven laminates interleaved with Nylon 66 nanofibers was investigated. Furthermore, the impact behavior of GLARE aluminum-glass epoxy laminates, toughened with Nylon 66 nanofibers was investigated. Finally, the possibility of confer to the composite material the capability of self-repair was explored. An extrinsic self-healing-system, based on core-shell nanofibers filled with a two-component epoxy system, was developed by co-electrospinning technique. The healing potential of the nano vascular system has been proved by microscope electron observation of the healing agent release as result of the vessels rupture and the crosslinking reaction was verified by thermal analysis.

Probabilistic Action System Trace Semantics

Action systems are a construct for reasoning about concurrent, reactive systems, in which concurrent behaviour is described by interleaving atomic actions. Sere and Troubitsyna have proposed an extension to action systems in which actions may be expressed and composed using discrete probabilistic choice as well as demonic nondeterministic choice. In this paper we develop a trace-based semantics for probabilistic action systems. This semantics provides a simple theoretical base on which practical refinement rules for probabilistic action systems may be justified.

Constraint reasoning with local search for continuous optimization

Optimization is a very important field for getting the best possible value for the optimization function. Continuous optimization is optimization over real intervals. There are many global and local search techniques. Global search techniques try to get the global optima of the optimization problem. However, local search techniques are used more since they try to find a local minimal solution within an area of the search space. In Continuous Constraint Satisfaction Problems (CCSP)s, constraints are viewed as relations between variables, and the computations are supported by interval analysis. The continuous constraint programming framework provides branch-and-prune algorithms for covering sets of solutions for the constraints with sets of interval boxes which are the Cartesian product of intervals. These algorithms begin with an initial crude cover of the feasible space (the Cartesian product of the initial variable domains) which is recursively refined by interleaving pruning and branching steps until a stopping criterion is satisfied. In this work, we try to find a convenient way to use the advantages in CCSP branchand- prune with local search of global optimization applied locally over each pruned branch of the CCSP. We apply local search techniques of continuous optimization over the pruned boxes outputted by the CCSP techniques. We mainly use steepest descent technique with different characteristics such as penalty calculation and step length. We implement two main different local search algorithms. We use “Procure”, which is a constraint reasoning and global optimization framework, to implement our techniques, then we produce and introduce our results over a set of benchmarks.

Rely-guarantee protocols for safe interference over shared memory

Mutable state can be useful in certain algorithms, to structure programs, or for efficiency purposes. However, when shared mutable state is used in non-local or nonobvious ways, the interactions that can occur via aliases to that shared memory can be a source of program errors. Undisciplined uses of shared state may unsafely interfere with local reasoning as other aliases may interleave their changes to the shared state in unexpected ways. We propose a novel technique, rely-guarantee protocols, that structures the interactions between aliases and ensures that only safe interference is possible. We present a linear type system outfitted with our novel sharing mechanism that enables controlled interference over shared mutable resources. Each alias is assigned separate, local roles encoded in a protocol abstraction that constrains how an alias can legally use that shared state. By following the spirit of rely-guarantee reasoning, our rely-guarantee protocols ensure that only safe interference can occur but still allow many interesting uses of shared state, such as going beyond invariant and monotonic usages. This thesis describes the three core mechanisms that enable our type-based technique to work: 1) we show how a protocol models an alias’s perspective on how the shared state evolves and constrains that alias’s interactions with the shared state; 2) we show how protocols can be used while enforcing the agreed interference contract; and finally, 3) we show how to check that all local protocols to some shared state can be safely composed to ensure globally safe interference over that shared memory. The interference caused by shared state is rooted at how the uses of di↵erent aliases to that state may be interleaved (perhaps even in non-deterministic ways) at run-time. Therefore, our technique is mostly agnostic as to whether this interference was the result of alias interleaving caused by sequential or concurrent semantics. We show implementations of our technique in both settings, and highlight their di↵erences. Because sharing is “first-class” (and not tied to a module), we show a polymorphic procedure that enables abstract compositions of protocols. Thus, protocols can be specialized or extended without requiring specific knowledge of the interference produce by other protocols to that state. We show that protocol composition can ensure safety even when considering abstracted protocols. We show that this core composition mechanism is sound, decidable (without the need for manual intervention), and provide an algorithm implementation.

Phase-sensitive dual-inversion recovery for accelerated carotid vessel wall imaging.

OBJECTIVES: Dual-inversion recovery (DIR) is widely used for magnetic resonance vessel wall imaging. However, optimal contrast may be difficult to obtain and is subject to RR variability. Furthermore, DIR imaging is time-inefficient and multislice acquisitions may lead to prolonged scanning times. Therefore, an extension of phase-sensitive (PS) DIR is proposed for carotid vessel wall imaging. METHODS: The statistical distribution of the phase signal after DIR is probed to segment carotid lumens and suppress their residual blood signal. The proposed PS-DIR technique was characterized over a broad range of inversion times. Multislice imaging was then implemented by interleaving the acquisition of 3 slices after DIR. Quantitative evaluation was then performed in healthy adult subjects and compared with conventional DIR imaging. RESULTS: Single-slice PS-DIR provided effective blood-signal suppression over a wide range of inversion times, enhancing wall-lumen contrast and vessel wall conspicuity for carotid arteries. Multislice PS-DIR imaging with effective blood-signal suppression is enabled. CONCLUSIONS: A variant of the PS-DIR method has successfully been implemented and tested for carotid vessel wall imaging. This technique removes timing constraints related to inversion recovery, enhances wall-lumen contrast, and enables a 3-fold increase in volumetric coverage at no extra cost in scanning time.

Bunch frequency multiplication by RF injection into an isochronous ring

La collaboration CLIC (Compact LInear Collider, collisionneur linéaire compact) étudie la possibilité de réaliser un collisionneur électron-positon linéaire à haute énergie (3 TeV dans le centre de masse) et haute luminosité (1034 cm-2s-1), pour la recherche en physique des particules. Le projet CLIC se fonde sur l'utilisation de cavités accélératrices à haute fréquence (30 GHz). La puissance nécessaire à ces cavités est fournie par un faisceau d'électrons de basse énergie et de haute intensité, appelé faisceau de puissance, circulant parallèlement à l'accélérateur linéaire principal (procédé appelé « Accélération à Double Faisceau »). Dans ce schéma, un des principaux défis est la réalisation du faisceau de puissance, qui est d'abord généré dans un complexe accélérateur à basse fréquence, puis transformé pour obtenir une structure temporelle à haute fréquence nécessaire à l'alimentation des cavités accélératrices de l'accélérateur linéaire principal. La structure temporelle à haute fréquence des paquets d'électrons est obtenue par le procédé de multiplication de fréquence, dont la manipulation principale consiste à faire circuler le faisceau d'électrons dans un anneau isochrone en utilisant des déflecteurs radio-fréquence (déflecteurs RF) pour injecter et combiner les paquets d'électrons. Cependant, ce type de manipulation n'a jamais été réalisé auparavant et la première phase de la troisième installation de test pour CLIC (CLIC Test Facility 3 ou CTF3) a pour but la démonstration à faible charge du procédé de multiplication de fréquence par injection RF dans un anneau isochrone. Cette expérience, qui a été réalisée avec succès au CERN au cours de l'année 2002 en utilisant une version modifiée du pré-injecteur du grand collisionneur électron-positon LEP (Large Electron Positron), est le sujet central de ce rapport. L'expérience de combinaison des paquets d'électrons consiste à accélérer cinq impulsions dont les paquets d'électrons sont espacés de 10 cm, puis à les combiner dans un anneau isochrone pour obtenir une seule impulsion dont les paquets d'électrons sont espacés de 2 cm, multipliant ainsi la fréquence des paquets d'électrons, ainsi que la charge par impulsion, par cinq. Cette combinaison est réalisée au moyen de structures RF résonnantes sur un mode déflecteur, qui créent dans l'anneau une déformation locale et dépendante du temps de l'orbite du faisceau. Ce mécanisme impose plusieurs contraintes de dynamique de faisceau comme l'isochronicité, ainsi que des tolérances spécifiques sur les paquets d'électrons, qui sont définies dans ce rapport. Les études pour la conception de la Phase Préliminaire du CTF3 sont détaillées, en particulier le nouveau procédé d'injection avec les déflecteurs RF. Les tests de haute puissance réalisés sur ces cavités déflectrices avant leur installation dans l'anneau sont également décrits. L'activité de mise en fonctionnement de l'expérience est présentée en comparant les mesures faites avec le faisceau aux simulations et calculs théoriques. Finalement, les expériences de multiplication de fréquence des paquets d'électrons sont décrites et analysées. On montre qu'une très bonne efficacité de combinaison est possible après optimisation des paramètres de l'injection et des déflecteurs RF. En plus de l'expérience acquise sur l'utilisation de ces déflecteurs, des conclusions importantes pour les futures activités CTF3 et CLIC sont tirées de cette première démonstration de la multiplication de fréquence des paquets d'électrons par injection RF dans un anneau isochrone.<br/><br/>The Compact LInear Collider (CLIC) collaboration studies the possibility of building a multi-TeV (3 TeV centre-of-mass), high-luminosity (1034 cm-2s-1) electron-positron collider for particle physics. The CLIC scheme is based on high-frequency (30 GHz) linear accelerators powered by a low-energy, high-intensity drive beam running parallel to the main linear accelerators (Two-Beam Acceleration concept). One of the main challenges to realize this scheme is to generate the drive beam in a low-frequency accelerator and to achieve the required high-frequency bunch structure needed for the final acceleration. In order to provide bunch frequency multiplication, the main manipulation consists in sending the beam through an isochronous combiner ring using radio-frequency (RF) deflectors to inject and combine electron bunches. However, such a scheme has never been used before, and the first stage of the CLIC Test Facility 3 (CTF3) project aims at a low-charge demonstration of the bunch frequency multiplication by RF injection into an isochronous ring. This proof-of-principle experiment, which was successfully performed at CERN in 2002 using a modified version of the LEP (Large Electron Positron) pre-injector complex, is the central subject of this report. The bunch combination experiment consists in accelerating in a linear accelerator five pulses in which the electron bunches are spaced by 10 cm, and combining them in an isochronous ring to obtain one pulse in which the electron bunches are spaced by 2 cm, thus achieving a bunch frequency multiplication of a factor five, and increasing the charge per pulse by a factor five. The combination is done by means of RF deflecting cavities that create a time-dependent bump inside the ring, thus allowing the interleaving of the bunches of the five pulses. This process imposes several beam dynamics constraints, such as isochronicity, and specific tolerances on the electron bunches that are defined in this report. The design studies of the CTF3 Preliminary Phase are detailed, with emphasis on the novel injection process using RF deflectors. The high power tests performed on the RF deflectors prior to their installation in the ring are also reported. The commissioning activity is presented by comparing beam measurements to model simulations and theoretical expectations. Eventually, the bunch frequency multiplication experiments are described and analysed. It is shown that the process of bunch frequency multiplication is feasible with a very good efficiency after a careful optimisation of the injection and RF deflector parameters. In addition to the experience acquired in the operation of these RF deflectors, important conclusions for future CTF3 and CLIC activities are drawn from this first demonstration of the bunch frequency multiplication by RF injection into an isochronous ring.<br/><br/>La collaboration CLIC (Compact LInear Collider, collisionneur linéaire compact) étudie la possibilité de réaliser un collisionneur électron-positon linéaire à haute énergie (3 TeV) pour la recherche en physique des particules. Le projet CLIC se fonde sur l'utilisation de cavités accélératrices à haute fréquence (30 GHz). La puissance nécessaire à ces cavités est fournie par un faisceau d'électrons de basse énergie et de haut courant, appelé faisceau de puissance, circulant parallèlement à l'accélérateur linéaire principal (procédé appelé « Accélération à Double Faisceau »). Dans ce schéma, un des principaux défis est la réalisation du faisceau de puissance, qui est d'abord généré dans un complexe accélérateur à basse fréquence, puis transformé pour obtenir une structure temporelle à haute fréquence nécessaire à l'alimentation des cavités accélératrices de l'accélérateur linéaire principal. La structure temporelle à haute fréquence des paquets d'électrons est obtenue par le procédé de multiplication de fréquence, dont la manipulation principale consiste à faire circuler le faisceau d'électrons dans un anneau isochrone en utilisant des déflecteurs radio-fréquence (déflecteurs RF) pour injecter et combiner les paquets d'électrons. Cependant, ce type de manipulation n'a jamais été réalisé auparavant et la première phase de la troisième installation de test pour CLIC (CLIC Test Facility 3 ou CTF3) a pour but la démonstration à faible charge du procédé de multiplication de fréquence par injection RF dans un anneau isochrone. L'expérience consiste à accélérer cinq impulsions, puis à les combiner dans un anneau isochrone pour obtenir une seule impulsion dans laquelle la fréquence des paquets d'électrons et le courant sont multipliés par cinq. Cette combinaison est réalisée au moyen de structures déflectrices RF qui créent dans l'anneau une déformation locale et dépendante du temps de la trajectoire du faisceau. Les résultats de cette expérience, qui a été réalisée avec succès au CERN au cours de l?année 2002 en utilisant une version modifiée du pré-injecteur du grand collisionneur électron-positon LEP (Large Electron Positon), sont présentés en détail.

Design and Analysis of Forward Error Control Coding and Signaling for Guaranteeing QoS in Wireless Broadcast Systems

Broadcasting systems are networks where the transmission is received by several terminals. Generally broadcast receivers are passive devices in the network, meaning that they do not interact with the transmitter. Providing a certain Quality of Service (QoS) for the receivers in heterogeneous reception environment with no feedback is not an easy task. Forward error control coding can be used for protection against transmission errors to enhance the QoS for broadcast services. For good performance in terrestrial wireless networks, diversity should be utilized. The diversity is utilized by application of interleaving together with the forward error correction codes. In this dissertation the design and analysis of forward error control and control signalling for providing QoS in wireless broadcasting systems are studied. Control signaling is used in broadcasting networks to give the receiver necessary information on how to connect to the network itself and how to receive the services that are being transmitted. Usually control signalling is considered to be transmitted through a dedicated path in the systems. Therefore, the relationship of the signaling and service data paths should be considered early in the design phase. Modeling and simulations are used in the case studies of this dissertation to study this relationship. This dissertation begins with a survey on the broadcasting environment and mechanisms for providing QoS therein. Then case studies present analysis and design of such mechanisms in real systems. The mechanisms for providing QoS considering signaling and service data paths and their relationship at the DVB-H link layer are analyzed as the first case study. In particular the performance of different service data decoding mechanisms and optimal signaling transmission parameter selection are presented. The second case study investigates the design of signaling and service data paths for the more modern DVB-T2 physical layer. Furthermore, by comparing the performances of the signaling and service data paths by simulations, configuration guidelines for the DVB-T2 physical layer signaling are given. The presented guidelines can prove useful when configuring DVB-T2 transmission networks. Finally, recommendations for the design of data and signalling paths are given based on findings from the case studies. The requirements for the signaling design should be derived from the requirements for the main services. Generally, these requirements for signaling should be more demanding as the signaling is the enabler for service reception.

Työntömastotrukkien tuotannon optimointi

Tutkimuksessa luodaan Tuko Logistics Oy:n työntömastotrukkien toimintaa opti-moivia toimintaehdotuksia varastonohjausjärjestelmästä saatavan työntömastotruk-kidatan pohjalta. Tutkimus on toteutettu haastattelututkimuksena ja käyttäen apuna tieteellisiä julkaisuja. Tehtävien lomittamistutkimuksen ja loogiseen päättelyn tulok-sena on luotu kaksi toimintaehdotusta: A ja B. Toimintaehdotusten vaikutuksia van-haan järjestelmään verrataan mittareilla, joista osa on tehty jonoteorian jonomallien laskukaavojen pohjalta. Mittareita ovat: tehdyt tehtävät tunnissa, tuottamattoman ajon suhde tuottavaan, normaalitehtäväjonon pituus ja normaalitehtäväjonon koko-naisodotusaika. Toimintaehdotus B osoittautuu tehokkaammaksi ehdotukseksi, mutta Toimintaehdotus A:lla voi varmistaa tehtävien riittämisen työntömastotrukeille. Tut-kimuksessa ehdotetaan myös muita työntömastotrukkien toimintaa optimoivia muu-toksia, jotka voidaan ottaa käyttöön jokaisessa toimintamallissa.

Active inverter output filtering methods

Frequency converters are widely used in the industry to enable better controllability and efficiency of variable speed AC motor drives. Despite these advantages, certain challenges concerning the inverter and motor interfacing have been present for decades. As insulated gate bipolar transistors entered the market, the inverter output voltage transition rate significantly increased compared with their predecessors. Inverters operate based on pulse width modulation of the output voltage, and the steep voltage edge fed by the inverter produces a motor terminal overvoltage. The overvoltage causes extra stress to the motor insulation, which may lead to a prematuremotor failure. The overvoltage is not generated by the inverter alone, but also by the sum effect of the motor cable length and the impedance mismatch between the cable and the motor. Many solutions have been shown to limit the overvoltage, and the mainstream products focus on passive filters. This doctoral thesis studies an alternative methodology for motor overvoltage reduction. The focus is on minimization of the passive filter dimensions, physical and electrical, or better yet, on operation without any filter. This is achieved by additional inverter control and modulation. The studied methods are implemented on different inverter topologies, varying in nominal voltage and current.For two-level inverters, the studied method is termed active du/dt. It consists of a small output LC filter, which is controlled by an independent modulator. The overvoltage is limited by a reduced voltage transition rate. For multilevel inverters, an overvoltage mitigation method operating without a passive filter, called edge modulation, is implemented. The method uses the capability of the inverter to produce two switching operations in the same direction to cancel the oscillating voltages of opposite phases. For parallel inverters, two methods are studied. They are both intended for two-level inverters, but the first uses individual motor cables from each inverter while the other topology applies output inductors. The overvoltage is reduced by interleaving the switching operations to produce a similar oscillation accumulation as with the edge modulation. The implementation of these methods is discussed in detail, and the necessary modifications to the control system of the inverter are presented. Each method is experimentally verified by operating industrial frequency converters with the modified control. All the methods are found feasible, and they provide sufficient overvoltage protection. The limitations and challenges brought about by the methods are discussed.

Limittelymenetelmän hyödyntäminen verkkovaihtosuuntaajassa: LCL-suotimen mitoitus

Teollisuudessa yleinen trendi on saada entistä tehokkaampia, halvempia, hyötysuhteeltaan parempia ja fyysisiltä mitoiltaan pienempiä sähkökäyttöjä. Luonnollisesti nämä vaatimukset ovat samoja myös taajuusmuuttajilla. Näiden vaatimusten välillä täytyy aina tehdä kompromisseja ja kehittää uusia menetelmiä. Monissa teollisuuden sähkökäytöissä tarvitaan verkkovaihtosuuntaajaa syöttämään tehoa generaattorilta tai jarrutettavalta moottorilta sähköverkkoon. Verkkovaihtosuuntaajassa käytännössä tarvitaan aina LCL-suodin, joka on fyysisesti järjestelmän suurin ja kallein yksittäinen komponentti, ja luonnollisesti suuritehoinen laite vaatii suuren LCL-suotimen. LCL-Suotimen fyysinen koko on kääntäen verrannollinen kytkentätaajuuteen. Tässä diplomityössä esitellään interleaving eli limittelymenetelmä, jonka avulla pystytään kasvattamaan verkkovaihtosuuntaajan ekvivalenttista kytkentätaajuutta ja pienentämään virran värettä sekä kokonaisharmonista säröä. Menetelmästä aiheutuu myös merkittävä haaste, kiertovirrat, joiden suodatusta tutkitaan kahdella eri menetelmällä. Käytetyt suodatustavat ovat LCL-suodin, jossa on lisäksi CM-kuristin ja LCL-suodin, jossa käytetään solujen välistä muuntajaa, ICT:tä. Työ suoritettiin teoriatutkimuksena ja simuloimalla. Tulokset osoittavat, että molemmat suodatustavat voivat toimia todellisessa sovelluksessa. Kuitenkin vain ICT:n omaava suodin on selkeästi vastaavan kokoista kaksitasoista verkkovaihtosuuntaajan suodinta pienempi. Tutkimus osoittaa myös sen, että tutkitussa sovelluskohteessa pelkkä fyysinen suodin ei riitä suodattamaan kiertovirtoja, vaan säätimeen täytyy tehdä myös muutoksia.

A Hierarchical Cache Coherent Protocol

As the number of processors in distributed-memory multiprocessors grows, efficiently supporting a shared-memory programming model becomes difficult. We have designed the Protocol for Hierarchical Directories (PHD) to allow shared-memory support for systems containing massive numbers of processors. PHD eliminates bandwidth problems by using a scalable network, decreases hot-spots by not relying on a single point to distribute blocks, and uses a scalable amount of space for its directories. PHD provides a shared-memory model by synthesizing a global shared memory from the local memories of processors. PHD supports sequentially consistent read, write, and test- and-set operations. This thesis also introduces a method of describing locality for hierarchical protocols and employs this method in the derivation of an abstract model of the protocol behavior. An embedded model, based on the work of Johnson[ISCA19], describes the protocol behavior when mapped to a k-ary n-cube. The thesis uses these two models to study the average height in the hierarchy that operations reach, the longest path messages travel, the number of messages that operations generate, the inter-transaction issue time, and the protocol overhead for different locality parameters, degrees of multithreading, and machine sizes. We determine that multithreading is only useful for approximately two to four threads; any additional interleaving does not decrease the overall latency. For small machines and high locality applications, this limitation is due mainly to the length of the running threads. For large machines with medium to low locality, this limitation is due mainly to the protocol overhead being too large. Our study using the embedded model shows that in situations where the run length between references to shared memory is at least an order of magnitude longer than the time to process a single state transition in the protocol, applications exhibit good performance. If separate controllers for processing protocol requests are included, the protocol scales to 32k processor machines as long as the application exhibits hierarchical locality: at least 22% of the global references must be able to be satisfied locally; at most 35% of the global references are allowed to reach the top level of the hierarchy.