Emulator as body schema

Grush's emulator model appears to be consistent with the idea of a body schema, that is, a detailed mental representation of the body, its structure. and movement in relation to the environment. If the emulator is equivalent to a body schema, then the next step will be to specify how the einulator accounts for neuropsychological and developmental phenornena that have long been hypothesized to involve the body schema.

A generator of efficient abstract machine implementations and its application to emulator minimization

The implementation of abstract machines involves complex decisions regarding, e.g., data representation, opcodes, or instruction specialization levéis, all of which affect the final performance of the emulator and the size of the bytecode programs in ways that are often difficult to foresee. Besides, studying alternatives by implementing abstract machine variants is a time-consuming and error-prone task because of the level of complexity and optimization of competitive implementations, which makes them generally difficult to understand, maintain, and modify. This also makes it hard to genérate specific implementations for particular purposes. To ameliorate those problems, we propose a systematic approach to the automatic generation of implementations of abstract machines. Different parts of their definition (e.g., the instruction set or the infernal data and bytecode representation) are kept sepárate and automatically assembled in the generation process. Alternative versions of the abstract machine are therefore easier to produce, and variants of their implementation can be created mechanically, with specific characteristics for a particular application if necessary. We illustrate the practicality of the approach by reporting on an implementation of a generator of production-quality WAMs which are specialized for executing a particular fixed (set of) program(s). The experimental results show that the approach is effective in reducing emulator size.

Assessing an FPGA implemented MIMO testbed with the use of channel emulator

In this paper, a channel emulator for assessing the performance of MIMO testbed implemented in a field programmable gate array technology is described. The FPGA based MIMO system includes a signal generator, modulation/demodulation and space time coding/decoding modules. The emulator uses information about a wireless channel from computer simulations or actual measurements. In simulations, a single bounce scattering model for an indoor environment is applied. The generated data is stored in the FPGA board. The tests are performed for a 2times2 MIMO system that uses Alamouti scheme for space coding/decoding. The performed tests show proper operation of the FPGA implemented MIMO testbed. Good agreement between the results using measured and simulated channel data is obtained.

VisibleZ: A Mainframe Architecture Emulator for Computing Education

This paper describes a PC-based mainframe computer emulator called VisibleZ and its use in teaching mainframe Computer Organization and Assembly Programming classes. VisibleZ models IBM’s z/Architecture and allows direct interpretation of mainframe assembly language object code in a graphical user interface environment that was developed in Java. The VisibleZ emulator acts as an interactive visualization tool to simulate enterprise computer architecture. The provided architectural components include main storage, CPU, registers, Program Status Word (PSW), and I/O Channels. Particular attention is given to providing visual clues to the user by color-coding screen components, machine instruction execution, and animation of the machine architecture components. Students interact with VisibleZ by executing machine instructions in a step-by-step mode, simultaneously observing the contents of memory, registers, and changes in the PSW during the fetch-decode-execute machine instruction cycle. The object-oriented design and implementation of VisibleZ allows students to develop their own instruction semantics by coding Java for existing specific z/Architecture machine instructions or design and implement new machine instructions. The use of VisibleZ in lectures, labs, and assignments is described in the paper and supported by a website that hosts an extensive collection of related materials. VisibleZ has been proven a useful tool in mainframe Assembly Language Programming and Computer Organization classes. Using VisibleZ, students develop a better understanding of mainframe concepts, components, and how the mainframe computer works. ACM Computing Classification System (1998): C.0, K.3.2.

A PV panel simulator based on a two quadrant DC/DC power converter with a sliding mode controller

The use of a solar photovoltaic (PV) panel simulator can be a valued tool for the design and evaluation of the several components of a photovoltaic system. This simulator is based on power electronic converter controlled in such a way that will behave as a PV panel. Thus, in this paper a PV panel simulator based on a two quadrant DC/DC power converter is proposed. This topology will allow to achieve fast responses, like suddenly changes in the irradiation and temperature. To control the power converter it will be used a fast and robust sliding mode controller. Therefore, with the proposed system I-V curve simulation of a PV panel is obtained. Experimental results from a laboratory prototype are presented in order to confirm the theoretical operation.

Emulador del Microcontrolador : Texas Instruments MSP430

Implementació d'un emulador del microcontrolador MSP430 de Texas Instruments. S'implementa l'emulació no només de la CPU, sinó també d'una part dels mòduls i els perifèrics integrats en el microcontrolador.

ATS3-testausjärjestelmän evaluointi

Työ tehtiin Nokia Technology Platforms S60 Mobile Runtime-yksikölle. Työn tavoitteena oli evaluoida ATS3-testausjärjestelmä. ATS3-järjestelmällä voidaan automatisoida ohjelmistotestausta. Evaluoinnilla pyrittiin selvittämään voidaanko tuotekehitysvaiheessa oleva järjestelmä ottaa jo käyttöön vai vaatiiko se vielä lisäkehitystä. Työssä kerrotaan aluksi yleisesti ohjelmistotestauksesta. Siinä käydään läpi myös testausprosessin vaiheet sekä kerrotaan lyhyesti avuksi kehitetyistä työkaluista. Työssä kerrotaan myös ATS3-järjestelmän edeltäjien ominaisuuksista, sekä miten ne eroavat tarkastelun kohteena olevasta järjestelmästä. Varsinainen evaluointi alkoi tutustumalla ja asentamalla järjestelmä. Tämän jälkeen suoritettiin samat testit sekä ATS2.x-järjestelmässä että ATS3-järjestelmäss. Testauksen jälkeen analysoitiin testitulosten yhdenmukaisuuden perusteella, voidaanko siirtyä käyttömään ATS3-järjestelmää. Testitulokset olivat käytännässä yhdenmukaiset suoritettaessa testejä matkapuhelimessa, mutta emulaattoritestaus täytyi jättää väliin. Lukuisista yrityksistä sekä järjestelmän kehittäjän avusta huolimatta testejä ei onnistuttu suorittamaan ATS3-järjestelmän emulaattoriympäristössä. Näin ollen päädyttiin tulokseen, ettei järjestelmää voida ottaa vielä käytöön emulaattoritestauksessa, vaan se vaatii lisätutkimusta sekä perehtymistä järjestelmään.

Mobiilin työajanhallinnan ohjelmistokehitys

Työajan seuranta ja kohdistaminen oikeisiin kustannuslajeihin on yrityksen suorituskyvyn ja kasvun kannalta usein välttämättömyys. Tässä työssä tutkitaan mobiiliteknologioiden mahdollisuuksia ja soveltuvuutta tuottaa palveluita työajan hallinnointiin, valitaan sopiva arkkitehtuuri ja kehitetään Java ME –teknologialla prototyyppi, joka on helposti integroitavissa yrityksen nykyisiin palvelinpuolen järjestelmiin ja tietokantoihin. Työn sovellusosuudessa kuvataan prototyypin ohjelmoinnissa käytetyt työkalut, menetelmät, ongelmakohdat sekä niiden ratkaisut. Suunnitelluissa käyttötapauksissa tapahtumatiedot syötetään manuaalisesti puhelimen käyttöliittymän kautta tai automatisoidummin kerätään kustannuskohdistetietoa työkohteisiin sijoitetuista NFC-tageista. Työaikaleimaamista testattiin emulaattorilla ja oikealla matkapuhelimella. Lopputuloksena asiakkaan työajanhallinnan tapahtumat siirtyvät langattomasti ja reaaliaikaisesti yrityksen webpalvelimelle JSON-formaatissa.

Kestomagneettitahtikoneen emulointi digitaalisella signaaliprosessorilla

Sähkökäytön suunnittelussa säätöä voidaan testata useassa tapauksessa reaaliaikasimulaattorilla todellisen laitteiston sijaan. Monet reaaliaikasimulaatioiden perustana käytetyt algoritmit soveltuvat täysinohjatulle invertterisillalle. Eräissä sovelluksissa halutaan kuitenkin käyttää puoliksiohjattua siltaa. Puoliksiohjattulla sillalla mallin kausaalisuus voi kääntyä, mitä perinteiset reaaliaikasimulaattorit eivät pysty simuloimaan Tässä työssä oli tavoitteena kehittää reaaliaikasimulaattori puoliksiohjatulle kestomagneettitahtikonekäytölle. Emulaattoriin mallinnettiin todellisen käytön kestomagneettitahtikone ja invertterisilta. Simulaattori toteutettiin digitaaliselle signaaliprosessorille (DSP) ja mittauksiin liittyvät oheislaitteet mallinnettiin FPGA-piirille. Emulaattoriin liitettiin erillinen säätäjä, jota käytettiin myös todellisen sähkökäytön säätämiseen. Emulaattorilla ja todellisella käytöllä tehtyjä mittauksia verrattiin ja emuloimalla saadut tulokset vastasivat melko hyvin todellisesta käytöstä mitattuja.

Virtual technology and haptic interface solutions for design and control of mobile working machines

Commercially available haptic interfaces are usable for many purposes. However, as generic devices they are not the most suitable for the control of heavy duty mobile working machines like mining machines, container handling equipment and excavators. Alternative mechanical constructions for a haptic controller are presented and analysed. A virtual reality environment (VRE) was built to test the proposed haptic controller mechanisms. Verification of an electric motor emulating a hydraulic pump in the electro-hydraulic system of a mobile working machine is carried out. A real-time simulator using multi-body-dynamics based software with hardware-in-loop (HIL) setup was used for the tests. Recommendations for further development of a haptic controller and emulator electric motor are given.

A Model-Based Development and Verification Framework for Distributed System-on-Chip Architecture

The capabilities and thus, design complexity of VLSI-based embedded systems have increased tremendously in recent years, riding the wave of Moore’s law. The time-to-market requirements are also shrinking, imposing challenges to the designers, which in turn, seek to adopt new design methods to increase their productivity. As an answer to these new pressures, modern day systems have moved towards on-chip multiprocessing technologies. New architectures have emerged in on-chip multiprocessing in order to utilize the tremendous advances of fabrication technology. Platform-based design is a possible solution in addressing these challenges. The principle behind the approach is to separate the functionality of an application from the organization and communication architecture of hardware platform at several levels of abstraction. The existing design methodologies pertaining to platform-based design approach don’t provide full automation at every level of the design processes, and sometimes, the co-design of platform-based systems lead to sub-optimal systems. In addition, the design productivity gap in multiprocessor systems remain a key challenge due to existing design methodologies. This thesis addresses the aforementioned challenges and discusses the creation of a development framework for a platform-based system design, in the context of the SegBus platform - a distributed communication architecture. This research aims to provide automated procedures for platform design and application mapping. Structural verification support is also featured thus ensuring correct-by-design platforms. The solution is based on a model-based process. Both the platform and the application are modeled using the Unified Modeling Language. This thesis develops a Domain Specific Language to support platform modeling based on a corresponding UML profile. Object Constraint Language constraints are used to support structurally correct platform construction. An emulator is thus introduced to allow as much as possible accurate performance estimation of the solution, at high abstraction levels. VHDL code is automatically generated, in the form of “snippets” to be employed in the arbiter modules of the platform, as required by the application. The resulting framework is applied in building an actual design solution for an MP3 stereo audio decoder application.

Perception and haptics

For people with motion impairments, access to and independent control of a computer can be essential. Symptoms such as tremor and spasm, however, can make the typical keyboard and mouse arrangement for computer interaction difficult or even impossible to use. This paper describes three approaches to improving computer input effectivness for people with motion impairments. The three approaches are: (1) to increase the number of interaction channels, (2) to enhance commonly existing interaction channels, and (3) to make more effective use of all the available information in an existing input channel. Experiments in multimodal input, haptic feedback, user modelling, and cursor control are discussed in the context of the three approaches. A haptically enhanced keyboard emulator with perceptive capability is proposed, combining approaches in a way that improves computer access for motion impaired users.

Virtualization for cost-effective teaching of assembly language programming

A virtual system that emulates an ARM-based processor machine has been created to replace a traditional hardware-based system for teaching assembly language. The proposed virtual system integrates, in a single environment, all the development tools necessary to deliver introductory or advanced courses on modern assembly language programming. The virtual system runs a Linux operating system in either a graphical or console mode on a Windows or Linux host machine. No software licenses or extra hardware are required to use the virtual system, thus students are free to carry their own ARM emulator with them on a USB memory stick. Institutions adopting this, or a similar virtual system, can also benefit by reducing capital investment in hardware-based development kits and enable distance learning courses.

Projeto de um sistema emulador de escoamentos e vaso de separação primária

The purpose of this study was to develop a pilot plant which the main goal is to emulate a flow peak pressure in a separation vessel. Effect similar that is caused by the production in a slug flow in production wells equipped with the artificial lift method plunger lift. The motivation for its development was the need to test in a plant on a smaller scale, a new technique developed to estimate the gas flow in production wells equipped with plunger lift. To develop it, studies about multiphase flow effects, operation methods of artificial lift in plunger lift wells, industrial instrumentation elements, control valves, vessel sizing separators and measurement systems were done. The methodology used was the definition of process flowcharts, its parameters and how the effects needed would be generated for the success of the experiments. Therefore, control valves, the design and construction of vessels and the acquisition of other equipment used were defined. One of the vessels works as a tank of compressed air that is connected to the separation vessel and generates pulses of gas controlled by a on/off valve. With the emulator system ready, several control experiments were made, being the control of peak flow pressure generation and the flow meter the main experiments, this way, it was confirmed the efficiency of the plant usage in the problem that motivated it. It was concluded that the system is capable of generate effects of flow with peak pressure in a primary separation vessel. Studies such as the estimation of gas flow at the exit of the vessel and several academic studies can be done and tested on a smaller scale and then applied in real plants, avoiding waste of time and money.