« Roolle de la despence extraordinaire de l'Escurye du Roy, que monseigneur le duc de Bellegarde, pair et grand écuier de France, a commandé et ordonné estre faicte et paiée par maistre Pierre Maugis, conseiller, notaire et secrétaire du Roy,... tant à cause du mariage de madame la princesse de Galle, soeur de Sad. Majesté, à présent royne de la Grande-Bretagne, que pour l'entretenement de tout le train et équipage dont l'Escurie de lad. dame a esté composé, depuis son étatblissement, jusqu'au 22e jour de juing de ladicte année [1625], que lad. dame Royne s'est embarquée à Boullongne... ».

Le dernier feuillet du volume (fol. 39) est formé par l'« Eseroux de la despence de bouche de l'Escurie du Roy,... durant le mois de janvier 1639. »

Contribuição para o estudo do embarque de uma rede neural artificial em field programmable gate array (FPGA)

This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing