A 10-bit 2GHz current-steering CMOS D/A converter

This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

Phase noise and spur reduction in an array of direct digital synthesizers

Many applications, including communications, test and measurement, and radar, require the generation of signals with a high degree of spectral purity. One method for producing tunable, low-noise source signals is to combine the outputs of multiple direct digital synthesizers (DDSs) arranged in a parallel configuration. In such an approach, if all noise is uncorrelated across channels, the noise will decrease relative to the combined signal power, resulting in a reduction of sideband noise and an increase in SNR. However, in any real array, the broadband noise and spurious components will be correlated to some degree, limiting the gains achieved by parallelization. This thesis examines the potential performance benefits that may arise from using an array of DDSs, with a focus on several types of common DDS errors, including phase noise, phase truncation spurs, quantization noise spurs, and quantizer nonlinearity spurs. Measurements to determine the level of correlation among DDS channels were made on a custom 14-channel DDS testbed. The investigation of the phase noise of a DDS array indicates that the contribution to the phase noise from the DACs can be decreased to a desired level by using a large enough number of channels. In such a system, the phase noise qualities of the source clock and the system cost and complexity will be the main limitations on the phase noise of the DDS array. The study of phase truncation spurs suggests that, at least in our system, the phase truncation spurs are uncorrelated, contrary to the theoretical prediction. We believe this decorrelation is due to the existence of an unidentified mechanism in our DDS array that is unaccounted for in our current operational DDS model. This mechanism, likely due to some timing element in the FPGA, causes some randomness in the relative phases of the truncation spurs from channel to channel each time the DDS array is powered up. This randomness decorrelates the phase truncation spurs, opening the potential for SFDR gain from using a DDS array. The analysis of the correlation of quantization noise spurs in an array of DDSs shows that the total quantization noise power of each DDS channel is uncorrelated for nearly all values of DAC output bits. This suggests that a near N gain in SQNR is possible for an N-channel array of DDSs. This gain will be most apparent for low-bit DACs in which quantization noise is notably higher than the thermal noise contribution. Lastly, the measurements of the correlation of quantizer nonlinearity spurs demonstrate that the second and third harmonics are highly correlated across channels for all frequencies tested. This means that there is no benefit to using an array of DDSs for the problems of in-band quantizer nonlinearities. As a result, alternate methods of harmonic spur management must be employed.

Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.

基于MAX5307和DSP的多回路测控系统设计

提出了一种多回路测控系统的设计方案。该方案仅使用一个DSP(数字信号处理器)及一个多通道集成的D/A转换器件MAX5307,不仅同时保证了多个测控回路的实时性及控制精度,而且实现简单,成本低廉。文中结合实际系统,给出了其具体的硬件和软件实现。该方法具有广泛的适用性,对类似系统的设计具有参考价值。

Programming an FPGA to Emulate the Dynamics of DC Machines

This paper presents the programming an FPGA (Field Programmable Gate Array) to emulate the dynamics of DC machines. FPGA allows high speed real time simulation with high precision. The described design includes block diagram representation of DC machine, which contain all arithmetic and logical operations. The real time simulation of the machine in FPGA is controlled by user interfaces they are Keypad interface, LCD display on-line and digital to analog converter. This approach provides emulation of electrical machine by changing the parameters. Separately Exited DC machine implemented and experimental results are presented.

Digital color reproduction on color television monitors

Color displays used in image processing systems consist of a refresh memory buffer storing digital image data which are converted into analog signals to display an image by driving the primary color channels (red, green, and blue) of a color television monitor. The color cathode ray tube (CRT) of the monitor is unable to reproduce colors exactly due to phosphor limitations, exponential luminance response of the tube to the applied signal, and limitations imposed by the digital-to-analog conversion. In this paper we describe some computer simulation studies (using the U*V*W* color space) carried out to measure these reproduction errors. Further, a procedure to correct for color reproduction error due to the exponential luminance response (gamma) of the picture tube is proposed, using a video-lookup-table and a higher resolution digital-to-analog converter. It is found, on the basis of computer simulation studies, that the proposed gamma correction scheme is effective and robust with respect to variations in the assumed value of the gamma.

An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording

Low power consumption per channel and data rate minimization are two key challenges which need to be addressed in future generations of neural recording systems (NRS). Power consumption can be reduced by avoiding unnecessary processing whereas data rate is greatly decreased by sending spike time-stamps along with spike features as opposed to raw digitized data. Dynamic range in NRS can vary with time due to change in electrode-neuron distance or background noise, which demands adaptability. An analog-to-digital converter (ADC) is one of the most important blocks in a NRS. This paper presents an 8-bit SAR ADC in 0.13-mu m CMOS technology along with input and reference buffer. A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. The use of a ping-pong input sampling scheme is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the data rate, the A/D process is only enabled through the in-built background noise rejection logic to ensure that the noise is not processed. The ADC resolution can be adjusted from 8 to 1 bit in 1-bit step based on the input dynamic range. The ADC consumes 8.8 mu W from 1 V supply at 1 MS/s speed. It achieves effective number of bits of 7.7 bits and FoM of 42.3 fJ/conversion-step.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

Generating VHDL-AMS models of digital-to-analogue converters from MATLAB®/SIMULINK®

Today, the trend within the electronics industry is for the use of rapid and advanced simulation methodologies in association with synthesis toolsets. This paper presents an approach developed to support mixed-signal circuit design and analysis. The methodology proposed shows a novel approach to the problem of developing behvioural model descriptions of mixed-signal circuit topologies, by construction of a set of subsystems, that supports the automated mapping of MATLAB®/SIMULINK® models to structural VHDL-AMS descriptions. The tool developed, named MS 2SV, reads a SIMULINK® model file and translates it to a structural VHDL-AMS code. It also creates the file structure required to simulate the translated model in the System Vision™. To validate the methodology and the developed program, the DAC08, AD7524 and AD5450 data converters were studied and initially modelled in MATLAB®/ SIMULINK®. The VHDL-AMS code generated automatically by MS 2SV, (MATLAB®/SIMULINK® to System Vision™), was then simulated in the System Vision™. The simulation results show that the proposed approach, which is based on VHDL-AMS descriptions of the original model library elements, allows for the behavioural level simulation of complex mixed-signal circuits.

Ambiente computacional para projetos de sistemas com tecnologia mista

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Pré-regulador retificador boost com controle digital por valores médios, para sistema de iluminação fluorescente multi-lâmpadas, utilizando dispositivo FPGA e VHDL

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

On-line topographic analysis in the SEM

A novel method for on-line topographic analysis of rough surfaces in the SEM has been investigated. It utilises a digital minicomputer configured to act as a programmable scan generator and automatic focusing unit. The computer is coupled to the microscope through digital-to-analogue converters which enable it to generate ramp waveforms allowing the beam to be scanned over a small sub-region of the field under program control. A further digital-to-analogue converter regulates the current supply to the objective lens of the microscope. The video signal is sampled by means of an analogue-to-digital converter and the resultant binary code stored in the computer's memory as an array of numbers describing relative image intensity. Computations based on the intensity gradient of the image allow the objective lens current to be found for the in-focus condition, which may be related to the working distance through a previous calibration experiment. The sensitivity of the method for detecting small height changes is theoretically of the order of 1 μm. In practice the operator specifies features of interest by means of a mobile spot cursor injected into the SEM display screen, or he may scan the specimen at sub-regions corresponding to pre-determined points on a regular grid defined by him. The operation then proceeds under program control. | A novel method for on-line topographic analysis of rough surfaces in the SEM has been investigated. It utilizes a digital minicomputer configured to act as a programmable scan generator and automatic focusing unit. A further digital-to-analog converter regulates the current supply to the objective lens of the microscope. The video signal is sampled by means of an analog-to-digital converter and the resultant binary code stored in the computer's memory as an array of numbers describing relative image intensity. The sensitivity of the method for detecting small height changes is theroretically of the order of 1 mu m.

Methodology analysis of a computational tool used in electronic circuit design

This paper considers the importance of using a top-down methodology and suitable CAD tools in the development of electronic circuits. The paper presents an evaluation of the methodology used in a computational tool created to support the synthesis of digital to analog converter models by translating between different tools used in a wide variety of applications. This tool is named MS 2SV and works directly with the following two commercial tools: MATLAB/Simulink and SystemVision. Model translation of an electronic circuit is achieved by translating a mixed-signal block diagram developed in Simulink into a lower level of abstraction in VHDL-AMS and the simulation project support structure in SystemVision. The method validation was performed by analyzing the power spectral of the signal obtained by the discrete Fourier transform of a digital to analog converter simulation model. © 2011 IEEE.

Modulateurs intégrés sur silicium pour la transmission de signaux à modulation d'amplitude multi-niveau

Au cours des dernières années, la photonique intégrée sur silicium a progressé rapidement. Les modulateurs issus de cette technologie présentent des caractéristiques potentiellement intéressantes pour les systèmes de communication à courte portée. En effet, il est prévu que ces modulateurs pourront être opérés à des vitesses de transmission élevées, tout en limitant le coût de fabrication et la consommation de puissance. Parallèlement, la modulation d’amplitude multi-niveau (PAM) est prometteuse pour ce type de systèmes. Ainsi, ce travail porte sur le développement de modulateurs de silicium pour la transmission de signaux PAM. Dans le premier chapitre, les concepts théoriques nécessaires à la conception de modulateurs de silicium sont présentés. Les modulateurs Mach-Zehnder et les modulateurs à base de réseau de Bragg sont principalement abordés. De plus, les effets électro-optiques dans le silicium, la modulation PAM, les différents types d’électrodes intégrées et la compensation des distorsions par traitement du signal sont détaillés.Dans le deuxième chapitre, un modulateur Mach-Zehnder aux électrodes segmentées est présenté. La segmentation des électrodes permet la génération de signaux optiques PAM à partir de séquences binaires. Cette approche permet d’éliminer l’utilisation de convertisseur numérique-analogique en intégrant cette fonction dans le domaine optique, ce qui vise à réduire le coût du système de communication. Ce chapitre contient la description détaillée du modulateur, les résultats de caractérisation optique et de la caractérisation électrique, ainsi que les tests systèmes. De plus, les tests systèmes incluent l’utilisation de pré-compensation ou de post-compensation du signal sous la forme d’égalisation de la réponse en fréquence pour les formats de modulation PAM-4 et PAM-8 à différents taux binaires. Une vitesse de transmission de 30 Gb/s est démontrée dans les deux cas et ce malgré une limitation importante de la réponse en fréquence suite à l’ajout d’un assemblage des circuits radiofréquences (largeur de bande 3 dB de 8 GHz). Il s’agit de la première démonstration de modulation PAM-8 à l’aide d’un modulateur Mach-Zehnder aux électrodes segmentées. Finalement, les conclusions tirées de ce travail ont mené à la conception d’un deuxième modulateur Mach-Zehnder aux électrodes segmentées présentement en phase de test, dont les performances montrent un très grand potentiel. Dans le troisième chapitre, un modulateur à réseau de Bragg à deux sauts de phase est présenté. L’utilisation de réseaux de Bragg est une approche encore peu développée pour la modulation. En effet, la réponse spectrale de ces structures peut être contrôlée précisément, une caractéristique intéressante pour la conception de modulateurs. Dans ces travaux, nous proposons l’ajout de deux sauts de phase à un réseau de Bragg uniforme pour obtenir un pic de transmission dans la bande de réflexion de celui-ci. Ainsi, il est possible d’altérer l’amplitude du pic de transmission à l’aide d’une jonction pn. Comme pour le deuxième chapitre, ce chapitre inclut la description détaillée du modulateur, les résultats des caractérisations optique et électrique, ainsi que les tests systèmes. De plus, la caractérisation de jonctions pn à l’aide du modulateur à réseau de Bragg est expliquée. Des vitesses de transmission PAM-4 de 60 Gb/s et OOK de 55 Gb/s sont démontrées après la compensation des distorsions des signaux. À notre connaissance, il s’agit du modulateur à réseau de Bragg le plus rapide à ce jour. De plus, pour la première fois, les performances d’un tel modulateur s’approchent de celles des modulateurs de silicium les plus rapides utilisant des microrésonateurs en anneau ou des interféromètres Mach-Zehnder.