Wavelet Transform Codec for Fast Retrieval of Slices of 3D Objects

We propose a method to encode a 3D magnetic resonance image data and a decoder in such way that fast access to any 2D image is possible by decoding only the corresponding information from each subband image and thus provides minimum decoding time. This will be of immense use for medical community, because most of the PET and MRI data are volumetric data. Preprocessing is carried out at every level before wavelet transformation, to enable easier identification of coefficients from each subband image. Inclusion of special characters in the bit stream facilitates access to corresponding information from the encoded data. Results are taken by performing Daub4 along x (row), y (column) direction and Haar along z (slice) direction. Comparable results are achieved with the existing technique. In addition to that decoding time is reduced by 1.98 times. Arithmetic coding is used to encode corresponding information independently

Windows环境下用软件CODEC实现数字视频实时通信

讨论了Ｗｉｎｄｏｗｓ环境下利用软件编解码器实现视频压缩的方法和技巧，结合视频捕获和视频传输，以网络环境下机器人遥操作的实际应用为背景，给出了数字视频实时通信的编程实例。

Grayscale and colour image Codec based on matching pursuit in the spatio-frequency domain

This report presents and evaluates a novel idea for scalable lossy colour image coding with Matching Pursuit (MP) performed in a transform domain. The benefits of the idea of MP performed in the transform domain are analysed in detail. The main contribution of this work is extending MP with wavelets to colour coding and proposing a coding method. We exploit correlations between image subbands after wavelet transformation in RGB colour space. Then, a new and simple quantisation and coding scheme of colour MP decomposition based on Run Length Encoding (RLE), inspired by the idea of coding indexes in relational databases, is applied. As a final coding step arithmetic coding is used assuming uniform distributions of MP atom parameters. The target application is compression at low and medium bit-rates. Coding performance is compared to JPEG 2000 showing the potential to outperform the latter with more sophisticated than uniform data models for arithmetic coder. The results are presented for grayscale and colour coding of 12 standard test images.

Digital surveillance based on video CODEC System-on-a-Chip (SoC) platforms

Today, most conventional surveillance networks are based on analog system, which has a lot of constraints like manpower and high-bandwidth requirements. It becomes the barrier for today's surveillance network development. This dissertation describes a digital surveillance network architecture based on the H.264 coding/decoding (CODEC) System-on-a-Chip (SoC) platform. The proposed digital surveillance network architecture includes three major layers: software layer, hardware layer, and the network layer. The following outlines the contributions to the proposed digital surveillance network architecture. (1) We implement an object recognition system and an object categorization system on the software layer by applying several Digital Image Processing (DIP) algorithms. (2) For better compression ratio and higher video quality transfer, we implement two new modules on the hardware layer of the H.264 CODEC core, i.e., the background elimination module and the Directional Discrete Cosine Transform (DDCT) module. (3) Furthermore, we introduce a Digital Signal Processor (DSP) sub-system on the main bus of H.264 SoC platforms as the major hardware support system for our software architecture. Thus we combine the software and hardware platforms to be an intelligent surveillance node. Lab results show that the proposed surveillance node can dramatically save the network resources like bandwidth and storage capacity.

Performance analysis of secure unified communications in the VMware-based cloud

Unified communications as a service (UCaaS) can be regarded as a cost-effective model for on-demand delivery of unified communications services in the cloud. However, addressing security concerns has been seen as the biggest challenge to the adoption of IT services in the cloud. This study set up a cloud system via VMware suite to emulate hosting unified communications (UC), the integration of two or more real time communication systems, services in the cloud in a laboratory environment. An Internet Protocol Security (IPSec) gateway was also set up to support network-level security for UCaaS against possible security exposures. This study was aimed at analysis of an implementation of UCaaS over IPSec and evaluation of the latency of encrypted UC traffic while protecting that traffic. Our test results show no latency while IPSec is implemented with a G.711 audio codec. However, the performance of the G.722 audio codec with an IPSec implementation affects the overall performance of the UC server. These results give technical advice and guidance to those involved in security controls in UC security on premises as well as in the cloud.

Speed and Area Optimized Implementation of H.264 8X8 DCT Transform and Quantizer

H.264 is a video codec standard which delivers high resolution video even at low bit rates. To provide high throughput at low bit rates hardware implementations are essential. In this paper, we propose hardware implementations for speed and area optimized DCT and quantizer modules. To target above criteria we propose two architectures. First architecture is speed optimized which gives a high throughput and can meet requirements of 4096x2304 frame at 30 frames/sec. Second architecture is area optimized and occupies 2009 LUTs in Altera’s stratix-II and can meet the requirements of 1080HD at 30 frames/sec.

Hardware basado en FPGA para síntesis de audio mediante muestras grabadas y control MIDI

El objetivo de este proyecto es desarrollar una plataforma hardware capaz de sintetizar sonidos a partir de fragmentos grabados, y de ser controlado mediante un dispositivo MIDI. Para ello se utilizará: - una placa de prototipado que incluye un dispositivo programable (FPGA) y un CODEC para la grabación/reproducción de audio digital. - un teclado MIDI.

基于RFID的基带通信IP核的设计与仿真

分析基于射频识别(RFID)技术的系统基带通信过程,建立RFID基带传输模型,利用FPGA技术实现具有基带编解码、数据收发功能的通信IP核,介绍基于模块化思想的基带通信IP核的RTL设计方法,利用QuartusⅡ与Simulink工具进行系统仿真,仿真实验结果表明,该通信模块是有效的,能够为设计RFID通信系统提供高度集成的基带通信IP核。

UHF RFID 射频前端及其编解码设计

射频识别（Radio Frequency Identification，RFID）技术，是一种利用射频通信实现的非接触式的数据采集和自动识别技术（以下通称RFID技术）。而超高频射频识别技术（Ultra High Frequency RFID，UHF RFID）具有识别距离远、识别准确率高、识别速度快、抗干扰能力强等特点而成为当前研发的热点。UHF RFID读写器的难点就在于射频前端电路和基带编解码的设计，它们设计的好坏直接决定了读写器的性能好坏。 本文首先通过介绍UHF RFID读写器射频前端设计的基本原理，采用射频通用收发模块进行射频前端设计的方法，给出了以ADF7020收发芯片为核心的UHF RFID读写器的射频前端的整体设计和具体的实现电路，设计了包括射频收发电路、射频前端匹配电路、滤波电路、环行器电路、功率放大电路等。 其次根据EPC Gen-2的协议标准进行了UHF RFID读写器的基带编码解码的仿真设计，然后开发了以FPGA为核心的完整的数字基带硬件电路，实际调试表明整个基带编解码软件在硬件基带PCB板上运行状况良好，并能对EPC Gen-2的协议标准的命令进行正确的编码解码。 最后通过研究学习软件无线电的理论和开发方法，把UHF　RFID读写器的射频前端分成射频模拟前端和射频数字前端，给出了一种基于软件无线电思想的UHF RFID射频数字前端设计模型，并借助于SIMULINK中的信号处理工具箱对构建的数字前端的进行仿真验证，仿真结果验证了用软件无线电实现UHF RFID数字前端的可行性。

Hierarchical VHDL libraries for DSP ASIC design

Methods are presented for the rapid design of DSP ASICs based on the use of hierarchical VHDL libraries. These are portable across many silicon foundries and allow complex DSP silicon systems to be developed in a fraction of the time normally required. Resulting designs are highly competitive with ones created using conventional methods. The approach is illustrated by its application to ADPCM codec and DCT cores.

A Steganalysis System Utilizing Temporal Pixel Correlation Of HEVC Video

High Efficiency Video Coding (HEVC) is the most recent video codec coming after currently most popular H.264/MPEG4 codecs and has promising compression capabilities. It is conjectured that it will be a substitute for current video compression standards. However, to the best knowledge of the authors, none of the current video steganalysis methods designed or tested with HEVC video. In this paper, pixel domain steganography applied on HEVC video is targeted for the first time. Also, its the first paper that employs accordion unfolding transformation, which merges temporal and spatial correlation, in pixel domain video steganalysis. With help of the transformation, temporal correlation is incorporated into the system. Its demonstrated for three different feature sets that integrating temporal dependency substantially increased the detection accuracy.

Advanced side information creation techniques and framework for Wyner-Ziv video coding

Recently, several distributed video coding (DVC) solutions based on the distributed source coding (DSC) paradigm have appeared in the literature. Wyner-Ziv (WZ) video coding, a particular case of DVC where side information is made available at the decoder, enable to achieve a flexible distribution of the computational complexity between the encoder and decoder, promising to fulfill novel requirements from applications such as video surveillance, sensor networks and mobile camera phones. The quality of the side information at the decoder has a critical role in determining the WZ video coding rate-distortion (RD) performance, notably to raise it to a level as close as possible to the RD performance of standard predictive video coding schemes. Towards this target, efficient motion search algorithms for powerful frame interpolation are much needed at the decoder. In this paper, the RD performance of a Wyner-Ziv video codec is improved by using novel, advanced motion compensated frame interpolation techniques to generate the side information. The development of these type of side information estimators is a difficult problem in WZ video coding, especially because the decoder only has available some reference, decoded frames. Based on the regularization of the motion field, novel side information creation techniques are proposed in this paper along with a new frame interpolation framework able to generate higher quality side information at the decoder. To illustrate the RD performance improvements, this novel side information creation framework has been integrated in a transform domain turbo coding based Wyner-Ziv video codec. Experimental results show that the novel side information creation solution leads to better RD performance than available state-of-the-art side information estimators, with improvements up to 2 dB: moreover, it allows outperforming H.264/AVC Intra by up to 3 dB with a lower encoding complexity.

A double data rate (DDR) architecture for OFDM based wireless consumer devices

The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed the development of high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products, as demonstrated in Wireless-USB and Wireless-HDMI. However, these devices need high frequency clock rates, particularly for the OFDM, FFT and symbol processing sections resulting in high silicon cost and high electrical power. The high clock rates make hardware prototyping difficult and verification is therefore very important but costly. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture for implementation inside a OFDM baseband codec in order to reduce the high frequency clock rates by a complete factor of 2. The presented architecture has been implemented and tested for ECMA-368 (Wireless- USB context) resulting in a maximum clock rate of 264MHz instead of the expected 528MHz clock rate existing anywhere on the baseband codec die.