Review ["Telling the Evolutionary Time : Molecular Clocks and the Fossil Record" edited by Philip C. J. Donoghue and M. Paul Smith]

Determining the temporal scale of biological evolution has traditionally been the preserve of paleontology, with the timing of species originations and major diversifications all being read from the fossil record. However, the ages of the earliest (correctly identified) records will underestimate actual origins due to the incomplete nature of the fossil record and the necessity for lineages to have evolved sufficiently divergent morphologies in order to be distinguished. The possibility of inferring divergence times more accurately has been promoted by the idea that the accumulation of genetic change between modern lineages can be used as a molecular clock (Zuckerkandl and Pauling, 1965). In practice, though, molecular dates have often been so old as to be incongruent even with liberal readings of the fossil record. Prominent examples include inferred diversifications of metazoan phyla hundreds of millions of years before their Cambrian fossil record appearances (e.g., Nei et al., 2001) and a basal split between modern birds (Neoaves) that is almost double the age of their earliest recognizable fossils (e.g., Cooper and Penny, 1997).

Mitochondrial molecular clocks and the origin of the major Otocephalan clades (Pisces : Teleostei): A new insight

The Otocephala, a clade including ostariophysan and clupeomorph telcosts, represents about a quarter of total fish species diversity, with about 1000 gencra and more than 7000 species. A series of recent papers have defended that the origin of this clade

Energy recovery from high-frequency clocks using DC-DC converters

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.

Energy recycling from multigigahertz clocks using fully integrated switching converters

Large digital chips use a significant amount of energy to broadcast a low-skew, multigigahertz clock to millions of latches located throughout the chip. Every clock cycle, the large aggregate capacitance of the clock network is charged from the supply and then discharged to ground. Instead of wasting this stored energy, it is possible to recycle the energy by controlling its delivery to another part of the chip using an on-chip dc-dc converter. The clock driver and switching converter circuits share many compatible characteristics that allow them to be merged into a single design and fully integrated on-chip. Our buck converter prototype, manufactured in 90-nm CMOS, provides a proof-of-concept that clock network energy can be recycled to other parts of the chip, thus lowering overall energy consumption. It also confirms that monolithic multigigahertz switching converters utilizing zero-voltage switching can be implemented in deep-submicrometer CMOS. With multigigahertz operation, fully integrated inductors and capacitors use a small amount of chip area with low losses. Combining the clock driver with the power converter can share the large MOSFET drivers necessary as well as being energy and space efficient. We present an analysis of the losses which we confirm by experimentally comparing the merged circuit with a conventional clock driver. © 2012 IEEE.

Mitochondrial molecular clocks and the origin of the major Otocephalan clades (Pisces : Teleostei): A new insight

The Otocephala, a clade including ostariophysan and clupeomorph telcosts, represents about a quarter of total fish species diversity, with about 1000 gencra and more than 7000 species. A series of recent papers have defended that the origin of this clade and of its major groups may be significantly older than the oldest fossils of each of these groups suggest. Some of these recent papers explicitly defend a Pangean origin for some otocephalan groups Such as the Siluriformes or Cypriniformes. To know whether or not the otocephalans as a whole, and particularly the mainly freshwater, cosmopolitan otophysans could have originated before the splitting of the Pangean Supercontinent is of extreme importance, since otophysan fishes are among the most useful animal groups for the determination of historical continental relationships. In the present work we examined divergence times for each major otocephalan group by an analysis of complete mtDNA sequences, in order to investigate if these divergence times support the hypotheses advanced in recent studies. The complete mtDNA sequences of nine representative non-otocephalan fish species and of twenty-one representative otocephalan species was compared. The present study is thus, among the studies dealing with molecular divergence times of telcosts, the one in which a greater number of otocephalan species are included. The divergence times obtained support that the major otocephalan groups had a much older origin than the oldest fossil records available for these groups suggest. The origin of the Otocephala is estimated as having occurred about 282 Mya, with the origin of the Otophysi being estimated at about 251 Mya. (c) 2005 Elsevier B.V. All rights reserved.

An estimate of divergence time of parazoa and eumetazoa and that of cephalochordata and vertebrata by aldolase and triose phosphate isomerase clocks

Previously we suggested that four proteins including aldolase and triose phosphate isomerase (TPI) evolved with approximately constant rates over long periods covering the whole animal phyla. The constant rates of aldolase and TPI evolution were reexamined based on three different models for estimating evolutionary distances, It was shown that the evolutionary rates remain essentially unchanged in comparisons not only between different classes of vertebrates but also between vertebrates and arthropods and even between animals and plants, irrespective of the models used, Thus these enzymes might be useful molecular clocks for inferring divergence times of animal phyla, To know the divergence time of Parazoa and Eumetazoa and that of Cephalochordata and Vertebrata, the aldolase cDNAs from Ephydatia fluviatilis, a freshwater sponge, and the TPI cDNAs from Ephydatia fluviatilis and Branchiostoma belcheri an amphioxus, have been cloned and sequenced, Comparisons of the deduced amino acid sequences of aldolase and TPI from the freshwater sponge with known sequences revealed that the Parazoa-Eumetazoa split occurred about 940 million years ago (Ma) as determined by the average of two proteins and three models, Similarly, the aldolase and TPI clocks suggest that vertebrates and amphioxus last shared a common ancestor around 700 Ma and they possibly diverged shortly after the divergence of deuterostomes and protostomes.

Large Scale Verification of MPI Programs Using Lamport Clocks with Lazy Update

We propose a dynamic verification approach for large-scale message passing programs to locate correctness bugs caused by unforeseen nondeterministic interactions. This approach hinges on an efficient protocol to track the causality between nondeterministic message receive operations and potentially matching send operations. We show that causality tracking protocols that rely solely on logical clocks fail to capture all nuances of MPI program behavior, including the variety of ways in which nonblocking calls can complete. Our approach is hinged on formally defining the matches-before relation underlying the MPI standard, and devising lazy update logical clock based algorithms that can correctly discover all potential outcomes of nondeterministic receives in practice. can achieve the same coverage as a vector clock based algorithm while maintaining good scalability. LLCP allows us to analyze realistic MPI programs involving a thousand MPI processes, incurring only modest overheads in terms of communication bandwidth, latency, and memory consumption. © 2011 IEEE.

Receipt from J.B. Fowler for clocks

Receipt from J.B. Fowler for clocks, March 5, 1887.

Power performance with gated clocks of a pipelined Cordic Core

This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Virtex-based FPGA devices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic Core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops used when synthesized with FPGA logic resources.

A scheme for synchronizing clocks connected by a packet communication network

Consider a communication system in which a transmitter equipment sends fixed-size packets of data at a uniform rate to a receiver equipment. Consider also that these equipments are connected by a packet-switched network, which introduces a random delay to each packet. Here we propose an adaptive clock recovery scheme able of synchronizing the frequencies and the phases of these devices, within specified limits of precision. This scheme for achieving frequency and phase synchronization is based on measurements of the packet arrival times at the receiver, which are used to control the dynamics of a digital phase-locked loop. The scheme performance is evaluated via numerical simulations performed by using realistic parameter values. (C) 2011 Elsevier By. All rights reserved.