Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as-follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than uW; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.

Notes on analog-digital conversion techniques,

Mode of access: Internet.

An Analog-to-digital conversion supervision for the IBM 1800,

"Supported in part by National Science Foundation Grant No. NSF-GP-7634."

Use of chart readers for analog to digital conversion of hydrologic data /

Mode of access: Internet.

GSPS photonic analogue to digital conversion system using broadband continuous wave source

An 80 GSPS photonic ADC system is demonstrated, using broadband MLL and dispersive fibre to form a continuous waveform with time-wavelength mapping, and AWG to channelise. Tests are carried out for RF signals up to 10GHz. © 2005 Optical Society of America.

80 GSPS photonic analogue to digital conversion system using broadband continuous wave source

An 80 GSPS photonic ADC system is demonstrated, using broadband MLL and dispersive fibre to form a continuous waveform with time-wavelength mapping, and AWG to channelise. Tests are carried out for RF signals up to 10GHz. © 2005 Optical Society of America.

Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.

Frequency synthesizer using a hybrid analog/digital loop filter: A low complexity approach

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Ach, analog, digital - Quanten! Blitzkurs für alle Feinde des Digitalen und Technologieverächter

Die Natur integriert digitale und analoge Systeme umstandslos, man muss nur auf die Welt der Quantenmechanik schauen. Warum also diese Dauerproduktion gesellschaftlicher und kultureller Endzeitszenarien? Warum die Dauerbeschwörung der digitalen Bedrohung? Warum lassen wir uns nicht einfach auf das ein, was unsere physikalische Existenz grundlegend determiniert — die Koexistenz.

Graphical processing using hybrid analog-digital circuitry,

Bibliography: p. 74.

Digital Conversion and Media Reformatting: Management and Production of Digital Collections

The Digital Conversion and Media Reformatting plan was written in 2012 and revised 2013-2014, as a five-year plan for the newly established department at the University of Maryland Libraries under the Digital Systems and Stewardship Division. The plan focuses on increasing digitization production, both in-house and through vendors, and creates a model for the management of this production.

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.