Application of lean production to reducing operational waste in a tile manufacturing process

Roofing tile manufacturing is a mass production process with high operational and inventory wastes and costs. Due to huge operational costs, excessive inventory and wastes, and quality problems, roofing tile manufacturers are trying to implement lean manufacturing practice in their operations in order to remain competitive in an ncreasingly competitive global market. The aim of this research is to evaluate the possibility of reducing the operational and inventory costs of the tile manufacturing process through waste minimization. This paper analyses the current waste situation in a tile manufacturing process and develops current and future value stream mapping for such a process with a view to implementing lean principles in manufacturing. The focus of the approach is on cost reduction by eliminating non-value-added activities.

Rack Level Modeling of Air Flow Through Perforated Tile in a Data Center

Effective air flow distribution through perforated tiles is required to efficiently cool servers in a raised floor data center. We present detailed computational fluid dynamics (CFD) modeling of air flow through a perforated tile and its entrance to the adjacent server rack. The realistic geometrical details of the perforated tile, as well as of the rack are included in the model. Generally, models for air flow through perforated tiles specify a step pressure loss across the tile surface, or porous jump model based on the tile porosity. An improvement to this includes a momentum source specification above the tile to simulate the acceleration of the air flow through the pores, or body force model. In both of these models, geometrical details of tile such as pore locations and shapes are not included. More details increase the grid size as well as the computational time. However, the grid refinement can be controlled to achieve balance between the accuracy and computational time. We compared the results from CFD using geometrical resolution with the porous jump and body force model solution as well as with the measured flow field using particle image velocimetry (PIV) experiments. We observe that including tile geometrical details gives better results as compared to elimination of tile geometrical details and specifying physical models across and above the tile surface. A modification to the body force model is also suggested and improved results were achieved.

Crystals that count! Physical principles and experimental investigations of DNA tile self-assembly

Algorithmic DNA tiles systems are fascinating. From a theoretical perspective, they can result in simple systems that assemble themselves into beautiful, complex structures through fundamental interactions and logical rules. As an experimental technique, they provide a promising method for programmably assembling complex, precise crystals that can grow to considerable size while retaining nanoscale resolution. In the journey from theoretical abstractions to experimental demonstrations, however, lie numerous challenges and complications.

In this thesis, to examine these challenges, we consider the physical principles behind DNA tile self-assembly. We survey recent progress in experimental algorithmic self-assembly, and explain the simple physical models behind this progress. Using direct observation of individual tile attachments and detachments with an atomic force microscope, we test some of the fundamental assumptions of the widely-used kinetic Tile Assembly Model, obtaining results that fit the model to within error. We then depart from the simplest form of that model, examining the effects of DNA sticky end sequence energetics on tile system behavior. We develop theoretical models, sequence assignment algorithms, and a software package, StickyDesign, for sticky end sequence design.

As a demonstration of a specific tile system, we design a binary counting ribbon that can accurately count from a programmable starting value and stop growing after overflowing, resulting in a single system that can construct ribbons of precise and programmable length. In the process of designing the system, we explain numerous considerations that provide insight into more general tile system design, particularly with regards to tile concentrations, facet nucleation, the construction of finite assemblies, and design beyond the abstract Tile Assembly Model.

Finally, we present our crystals that count: experimental results with our binary counting system that represent a significant improvement in the accuracy of experimental algorithmic self-assembly, including crystals that count perfectly with 5 bits from 0 to 31. We show some preliminary experimental results on the construction of our capping system to stop growth after counters overflow, and offer some speculation on potential future directions of the field.

A Synthesis Tool for a Tile-Based Heterogeneous FPGA

A multi-mode logic cell architecture in a tile-based heterogeneous FPGA is proposed, and a logic synthesis tool, called Vsyn, based on this architecture is presented. The logic cell architecture design and its synthesis tool development are strongly influencing each other. Any feature or parameter from one needs to be fully exercised and verified on the other. In this paper, we presented experimental results based MCNC benchmarks to show that the integration of the synthesis tool and the FPGA architecture can achieve high performance in the targeted FPGA applications. In addition, Vsyn can also target embedded special-purpose macros for the heterogeneous FPGA.

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

Printed blank of freight Notice for shipping from the Suspension Bridge to St. Catharines for tile

Printed blank of freight Notice for shipping from the Suspension Bridge to St. Catharines for tiles, Aug.6, 1875.